Improved successive-approximation analog-to-digital converter (ADC) circuits are undergoing development for eventual incorporation into focal-plane arrays of photodetectors. These circuits are derived from, and offer advantages over, the ones described in "Successive-Approximation ADCs With Charge Balancing" (NPO-19784), NASA Tech Briefs, Vol. 21, No. 5 (May 1997), page 47.
The top part of the figure shows a circuit of the previously reported type. The circuit implements successive-approximation analog-to-digital conversion according to a charge-balancing approach, in which the reset (R) and signal (S) branches of the circuit accumulate successively halved increments of reference charge in an attempt to balance the charges in the two branches. The circuit includes two high-gain charge-integrating operational amplifiers, the components of which must be closely matched to achieve accuracy in conversion. To achieve close matching, it is necessary to make the transistors in the amplifiers larger and to use dc bias currents larger than one would otherwise be inclined to do; as a consequence, the size and power consumption of the circuit are increased, making it more difficult to integrate the circuit into a high-performance focal-plane array of photodetector readout circuits.
The middle part of the figure shows a circuit at an intermediate stage of development, in which a single operational amplifier (instead of two high-gain operational amplifiers) is used to integrate charges on both the R and S branches during non-overlapping clock phases. Sharing of the same operational amplifier by both branches results in perfect matching of dc gain and dc offset, and in a large reduction of a component of ADC error associated with dc gain. However, the error caused by the matched dc offset is not necessarily small when the dc gain is low, which it can well be in some designs.
It turns out that the offset effect can be eliminated by replacing the single operational amplifier with a single autobiasing inverter. A dc gain of 40 dB is sufficient for 8-bit accuracy, and gain greater than 40 dB can be achieved via self-cascoding of the inverter transistors. The bottom part of the figure illustrates the resulting improved ADC circuit. In comparison with a circuit of the previously reported type, a circuit of the present type can be made to operate at the same rate and the same level of accuracy while occupying less space and consuming less power.
This work was done by Zhimin Zhou and Bedabrata Pain of Caltech for NASA's Jet Propulsion Laboratory.
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Refer to NPO-19979