A complementary metal oxide/semiconductor (CMOS) integrated-circuit video image detector of the active-pixel-sensor (APS) type has been designed to implement programmable multiresolution output (through summing of outputs from selected groups of neighboring pixels) in a low-power, high-speed, low-noise differential column-readout scheme. This scheme increases (relative to CMOS APS devices of older designs) the signal-to-noise ratios achievable under low illumination.

Summing of signals from neighboring pixels, also called "pixel binning," amounts to trading away spatial resolution to increase sensitivity or decrease noise. This concept was described in "Active-Pixel Image Sensors With Programmable Resolution" (NPO-19510), NASA Tech Briefs, Vol. 20, No. 5 (May 1996), page 26. Pixel binning was implemented previously in a CMOS APS designed for frame-transfer operation. That CMOS APS proved to be susceptible to pickup of extraneous noise and to high residual fixed pattern noise (FPN) due to the use of a single-ended column integrator circuit. Moreover, the pixel binning was implemented by use of a two-dimensional-array analog memory circuit that more than doubled the area of the APS integrated-circuit chip. The differential column-readout scheme of the present CMOS APS reduces both FPN and temporal circuit noise. This scheme also eliminates the need for a two-dimensional memory array, thereby facilitating the development of CMOS APS devices with greater numbers of pixels and higher speed of operation.

The Combination of Unique Design Features, namely, pixel binning, differential column readout, and the use of a single output buffer (global integrator) reduces output noise.

Like other typical CMOS APS devices, the present one comprises a two-dimensional array of photogates with active pixel and peripheral readout circuits. The selection of rows and columns for programming the dimensions and sequence of summation kernels is effected by use of externally generated control signals fed to row- and column-address decoders. The figure illustrates both the overall unique signal-processing architecture and the portion of the circuitry in the signal chain from one pixel to the output terminals.

To begin the pixel-summing process for a neighborhood of mby n pixels, each column integrator generates a sum of differential outputs from the pixels in the m selected contiguous rows in that column, in the following procedure: The signal (S) and reset (R) levels of each row are first sampled on the sample-and-hold capacitors CMS and CMR, respectively, as the column integrators are reset. Then the S and R levels are then differentially integrated on integrating capacitors CIS and CIR, respectively. The foregoing steps are repeated until the signals from all m rows in the neighborhood have been summed. The integrated levels are then sampled and held on the column memory capacitors CLS and CLR. A global integrator generates a differential output signal, one neighborhood at a time, by summing the signals from the memory capacitors of the n selected columns. The imager chip dissipates only 24 mW of power while running at 125 frames per second.

This work was done by Bedabrata Pain, Zhimin Zhou, and Eric Fossum of Caltech for NASA's Jet Propulsion Laboratory.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to

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Refer to NPO-20344