A unique data-acquisition system converts analog input voltages to 8-bit digital data at a rate as high as 109 samples per second (1 GHz), stores the data, and makes the data available for further processing. The system is compact, is highly resistant to ionizing radiation, consumes relatively little power, and is made from commercially available components. Designed for original use as part of a spaceborne laser altimeter, such data-acquisition systems could be adapted to potential terrestrial use as general-purpose high-speed analog-to-digital converters in electronic test equipment and scientific instruments, and as memory devices for storing data to be processed in digital signal-processing systems.

The major subsystems and functions of the system are as follows: The system includes an 8-bit, 1-GHz analog-to-digital converter (ADC), emitter-coupled logic (ECL) circuits to slow (as explained below) the data signals to 83.33 megasamples per second, programmable gate arrays that further slow the data signals for efficient writing, and a static random-access memory (SRAM) that stores the data. If the data are encoded (as explained below) then in making the stored data available for processing, the programmable gate arrays are also reused as decoders during readout from the SRAM.

The master clock signal for the system is a sinusoidal signal with a frequency of 2 GHz. This signal is processed through a 2:1 frequency divider to obtain a 1-GHz, 1/2-duty-cycle square wave, which serves as a timing signal for the ADC. In the ADC, the input signal that one seeks to process is digitized to 8 bits. The ADC internally demultiplexes the digital data signal into two 500-MHz ECL channels, each channel containing the 8 data bits plus a data-ready signal. ECL flip-flops and shift registers then slow the 500-MHz data signals from the two channels into 83 1/3-MHz signals in twelve channels.

The data signals in the twelve 83 1/3-MHz channels are converted from ECL to transistor/transistor logic (TTL) levels, then passed to programmable gate arrays. The gate arrays contain flip-flops that collect the data in groups of four bytes. The gate arrays also contain logic circuits that generate standard address, chip-selection, reading, and writing signals for storing the data in or reading data from the SRAM at a rate of 20.833 MHz. In addition, the gate arrays generate a signal that indicates when the SRAM is full.

Acquisition of data is enabled or disabled by a single digital input bit. When acquisition is not enabled, the gate arrays collectively serve as a portal through which a digital processor can read data from, and write data to, the SRAM by use of the processor's own address, chip-selection, reading, and writing signals. The data can be Gray-coded or Gray-decoded during such reading or writing. The data path between this system and a digital processor is 32 bits wide; this feature makes it possible for a high-performance processor to gain access to four data samples per transaction.

This work was done by Kenneth W. Wagner of Goddard Space Flight Center. GSC-14176

NASA Tech Briefs Magazine

This article first appeared in the October, 1999 issue of NASA Tech Briefs Magazine.

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