When a silicon wafer is cut from an ingot, it is essentially impossible to align the cut perfectly with the crystal structure. Therefore the surface contour of the wafer will be a flat plane on which terraces consisting of additional atomic layers will be scattered. An atomic step will be found on the surface where each additional layer is encountered. At elevated temperatures, these atomic steps will migrate, but they cannot be eliminated. At the current level of device technology, the effects of steps on the wafer surface can be largely ignored. In future generations of integrated circuits, however, the sizes of these steps will become comparable to some device feature sizes and will affect circuit performance and yields.
The method of the invention is to create a grid pattern on the surface of the wafer, dividing it into an array of squares separated by ridges. In the demonstration project, the squares ranged in dimension from 2 to 50 microns on each side, and the ridges were approximately 0.5 micron high and 1 micron wide. The wafer is then annealed at a temperature of between 1020 and 1150 °C. At the annealing temperature, the atomic steps migrate to and join with the ridges, leaving the square surface areas atomically flat. The dimensions and shapes of the step-free regions could be designed to accommodate particular device arrays.
This invention eliminates one of the major limitations in the further miniaturization of microelectronic devices through the commitment of only a small percentage of the area of the wafer ( ≤10 percent) to the grid pattern. It is able to accomplish this through technology that is currently available and easily implemented. Circuits built on step-free surfaces can be designed with smaller dimensions and utilize thinner semiconductor and insulation layers to increase performance and decrease power consumption.
Work continues to determine the maximum dimensions of the flattened areas and the optimum combination of annealing time and temperature. The processing time required depends on the initial quality of the surface. Development of alternative processes is under way. One alternative process uses trenches, rather than ridges, to separate the flattened areas, and deposition rather than evaporation. It will have the advantage of achieving these results at lower temperatures.
By providing a silicon substrate that is perfectly flat, this invention gives integrated circuit manufacturers the ideal surface on which to build devices. The inventive method does not require exotic equipment, unfamiliar processes, or high precision. The flattened areas on the wafer can be made large enough to accommodate an entire circuit. The remnants of the ridge regions involve only small slopes and hence do not present problems in interconnects. Circuit sizes can be decreased, and performance and production yields can be expected to increase. This process can be implemented in stages. After a processing cycle, wafers that do not meet specifications may be recycled until the desired results are achieved.
This work was done by Jack Blakeley, So Tanaka, C.C. Umbach, and Ruud Tromp at Cornell University . For more information, call Robert F. Schleelein, Technology Marketing and Licensing Specialist, Cornell Research Foundation Inc., 20 Thornwood Drive, Suite 105, Ithaca, NY 14850; (607) 257-1081; fax (607) 257-1015; E-mail: rfs4@cornell. edu; http://www.research.cornell.edu/crf.