A digital receiver in a 1.26-GHz spaceborne radar scatterometer now undergoing development includes a module for detecting radio-frequency interference (RFI) that could contam-inate scientific data intended to be acquired by the scatterometer. The role of the RFI-detection module is to identify time intervals during which the received signal is likely to be contaminated by RFI and thereby to enable exclusion, from further scientific data processing, of signal data acquired during those intervals. The underlying concepts of detection of RFI and rejection of RFI-contaminated signal data are also potentially applicable in advanced terrestrial radio receivers, including software-defined radio receivers in general, receivers in cellular telephones and other wireless consumer electronic devices, and receivers in automotive collision-avoidance radar systems.
The improvement afforded by the present RFI module is best seen against the background of prior scatterometer back-end receiver designs. It has been conventional practice to either (1) use analog square-law detection and integration at an intermediate frequency (IF) or (2) sample an echo having a bandwidth of no more than hundreds of kilohertz at base-band and then perform Fourier-transform and magnitude-squared calculations in digital processing. Both of these conventional practices provide accurate estimates of total received power, but they also destroy, through averaging, information on the signal statistics (especially, the voltage probability distribution) in each echo measurement. This is unfortunate because the statistical information can serve as an indication of whether the scatterometer is receiving only the desired reflections from a distributed natural target or is receiving interfering signals from artificial sources in addition to, or instead of, the desired reflections.
The RFI-detection module is part of a digital square-law scatterometer processor (SP) implemented in a field-programmable gate array (FPGA). The raw scatterometer output signal used to generate an input signal for the SP is a down-converted signal at offset video frequencies in the range from 2 to 6 MHz. This signal is alternated in time with either radar echo pulses or a receiver “noise-only” measurement signal. The video signal is processed by an analog-to-digital converter (ADC) at a sampling rate of 16 MHz (greater than the Nyquist sampling rate) before being sent to the SP FPGA. The main part of the SP calculates the signal power by use of square-and-accumulate logic during each successive receiving time window. At the same time, raw magnitude (absolute-value) information from the ADC is fed to the RFI-detection module at the full 16-MHz sampling rate.