These architectures are based on methods of vector processing and the discrete Fourier transform/inverse discrete Fourier transform (DFT-IDFT) overlap and save method, combined with time-block separation of digital filters into frequency-domain subfilters implemented by use of sub-convolutions. The parallel processing method implemented in these architectures enables the use of relatively small DFT-IDFT pairs, while filter tap lengths are theoretically unlimited. The size of a DFT-IDFT pair is determined by the desired reduction in processing rate, rather than on the order of the filter that one seeks to implement. A report presents additional information on the parallel, discrete-time, sub-convolution filtering architectures that lie at the heart of the innovation described in "Modular, Parallel, Efficient Pulse-Shaping Filters" (NPO-30186) elsewhere in this issue of NASA Tech Briefs. The emphasis in the report is on those aspects of the underlying theory and design rules that promote computational efficiency, parallel processing at reduced data rates, and simplification of the designs of very-large-scale integrated (VLSI) circuits needed to implement high-order filters and correlators.

This work was done by Andrew A. Gray of Caltech for NASA's Jet Propulsion Laboratory. To obtain a copy of the report, "Computationally Efficient Parallel Subconvolution Filtering Architectures," access the Technical Support Package (TSP) free on-line at under the Computers/Electronics category.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed toem>

Intellectual Property group
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109
(818) 354-2240

Refer to NPO-30142, volume and number of this NASA Tech Briefs issue, and the page number.