Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits.
The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely "Implementing Permutation Matrices by Use of Quantum Dots" (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; "Compact Interconnection Networks Based on Quantum Dots" (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; "Bit-Serial Adder Based on Quantum Dots" (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and "Hybrid VLSI/QCA Architecture for Computing FFTs" (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantum-mechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns.
Heretofore, researchers have recognized two major obstacles to realization of QCA-based logic gates: One is the need for (and the difficulty of attaining) operation of QCA circuitry at room temperature or, for that matter, at any temperature above a few Kelvins. It has been theorized that room-temperature operation could be made possible by constructing QCA as molecular-scale devices. However, in approaching the lower limit of miniaturization at the molecular level, it becomes increasingly imperative to overcome the second major obstacle, which is the need for (and the difficulty of attaining) high precision in the alignments of adjacent QCA in order to ensure the correct interactions among the quantum dots.
The fault-tolerant logic gates that would be implemented by blocks of QCA according to the proposal include majority and inverter (NOT) gates, which are said to be universal logic gates because other logic gates (AND, OR, and NOR) can be implemented as combinations of majority and inverter gates. The figure depicts examples of (1) a basic QCA majority gate manufactured with exact positioning of all QCA, (2) a basic QCA majority gate manufactured with a significant position error, (3) a block QCA gate manufactured with exact positioning, and (4) a block QCA gate manufactured with irregularity of positions in the QCA array and errors in the choice of the edge QCAs used for input. These and other examples were analyzed by computational simulation, using a program developed at the University of Notre Dame, that implements a Hartree-Fock mathematical model of the physics of a QCA array. The simulation was performed for an assumed cell size of 20 nm and inter-cell distance of 14 nm.
The results of the simulation showed that for a basic QCA majority gate, an output error would occur if the errors in the relative positions of adjacent cells were to exceed various amounts of the order of the size of a cell or a significant fraction thereof (the exact amounts being different for different cells and different directions of displacement). In the case of a molecular implementation, this would translate to a requirement for impractical sub-nanometer manufacturing tolerances. On the other hand, the simulation showed that even with errors as large as those depicted for the block majority gate at the bottom of the figure, there would be no output error.
Basic and Block QCA Majority Gates, with and without misalignments, were analyzed by computational simulation. The results of the analysis showed that, relative to the basic gate, the block gate would be more tolerant of manufacturing errors.
This work was done by Amir Firjany, Nikzad Toomarian, and Katayoon Modarres of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp under the Computers/Electronics category.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to
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Refer to NPO-21127, volume and number of this NASA Tech Briefs issue, and the page number.
This Brief includes a Technical Support Package (TSP).
Block QCA fault-tolerant logic gates
(reference NPO-21127) is currently available for download from the TSP library.
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