The return-link processor card (RLP) performs all of the fundamental data-processing functions involved in the return of satellite telemetry, in real time at rates up to 400 Mb/s, using industry-standard interface circuitry and connectors with standard sizes and shapes. Previously, four cards, each containing a central processing unit (CPU), were needed to do what the RLP now does. CPU-based cards are complex; are expensive to build, operate, and maintain; are susceptible to malfunction; and require a great deal of power and cooling.

Functions of the RLP include frame synchronization, cyclic-redundancy-code and bit-transition-density decoding, detection and correction of errors by use of Reed-Solomon codes, processing according to the Consultative Committee for Space Data Systems (CCSDS) standard for Advanced Orbiting Systems (AOS) service, and CCSDS conventional processing of packets and frames of telemetric data. The RLP can also synchronize frames of data in a weather-satellite-data format and in other formats. Data received via the Internet and other low-rate sources accessible by a computer can be injected directly by the host computer in which the RLP is installed.

The RLP is a single industry-standard peripheral component interface (PCI) expansion card. In addition to the industry-standard PCI connector, it contains industry-standard subminiature B connectors for emitter-coupled-logic (ECL) input, an industry-standard DB-9 connector for RS-422 input, connectors for programming nonvolatile logic devices and a connector for an optional sorting module (OSM — a mezzanine board on which additional buffering, processing, and output functions can be implemented.)

The RLP contains the following circuits:

  • An ECL input interface circuit,
  • An RS-422 input interface circuit,
  • A special-purpose parallel intgrated frame-synchronizing application specific integrated circuit (ASIC),
  • A special-purpose Reed-Solomon error-detecting-and-correcting ASIC,
  • A custom ASIC for CCSDS AOS Service and conventional CCSDS processing of packets and frames,
  • A PCI-bus-interface ASIC,
  • A custom direct-memory-access interface reprogrammable, non-volatile logic circuit,
  • A custom reprogrammable non-volatile logic circuit for monitoring and controlling the other circuits,
  • A custom reprogrammable non-volatile logic circuit that serves to collect status from the other circuits and supply it as a telemetry data stream, and
  • Miscellaneous active and passive devices.

During typical operation, a standard serial data stream enters via either the ECL or the RS-422 input path, is processed in data-flow fashion through the ASICs, and is deposited in a number of first-in/first-out (FIFO) memory buffers onboard the RLP. Setup, control, retrieval of data, and monitoring are performed through an entirely memory-mapped PCI interface by software running on the host computer. The presence of data can be detected either by use of interrupts or by polling. Monitoring information is semiautomatically collected into easy-to-retrieve data blocks.

In comparison with the previous assembly of four cards, the RLP is smaller, less expensive, faster, and more energy-efficient. The CPU-less, memory-mapped mode of operation of the RLP is simpler and more robust than was the CPU-based operation of the previous assembly. The RLP is more flexible in that it can operate in any industry-standard PCI host computer and all logic is implemented in reprogrammable nonvolatile logic devices. The RLP is also both more flexible and expandable by virtue of the OSM interface connector.

This work was done by Kenneth B. Winiecki, Jason Dowling, Stephen T. Koubek, and Fred H. Peng of Lockheed Martin and Andrew F. Wolf of RMS for Goddard Space Flight Center. For further information, access the Technical Support Package (TSP) free on-line at  under the Electronics & Computers category . GSC-14032

NASA Tech Briefs Magazine

This article first appeared in the January, 2000 issue of NASA Tech Briefs Magazine.

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