The forward-link/simulator card (FLS) performs the fundamental satellite-telemetry data-transmission function for the forward (Earth-to-spacecraft) link in real time at rates up to 400 Mb/s. The FLS also simulates a Consultative Committee for Space Data Systems (CCSDS) telemetry data source that outputs data at rates up to 150 Mb/s, using industry-standard interface circuitry and standard connectors. Previously, at least two cards, each containing a central processing unit (CPU), were needed to do what the FLS now does. CPU-based cards are complex; are expensive to build, operate, and maintain; are susceptible to malfunction; and require a great deal of power and cooling.

The FLS is a single industry-standard, full-length, 32-bit, 33-MHz, 5-V peripheral component interface (PCI) expansion card. In addition to the industry-standard PCI connector, it contains industry-standard subminiature B connectors for emitter-coupled-logic (ECL) input, an industry-standard DB-9 connector for RS-422 output, and a connector for programming nonvolatile logic devices. It contains an ECL output interface circuit, an RS-422 output interface circuit, a PCI bus interface application-specific integrated circuit (ASIC), three large reprogrammable nonvolatile logic devices, two large reprogrammable volatile logic devices, and miscellaneous active and passive devices.

In a typical data-source simulation, a test data pattern is loaded into a base pattern memory, control registers are set up by the host computer in which the FLS is installed and the card proceeds to generate test data automatically until it is stopped by the host computer. During typical forward-link operation, a pre-formatted uplink data stream, (comprising, for example, CCSDS telecommand frames), is loaded into a command buffer by the host, and the card proceeds to output the data automatically. Setup, control, insertion of data, and monitoring are performed through an entirely memory-mapped PCI interface by software running on the host computer.

In comparison with the previous assembly of at least two cards, the FLS is smaller, less expensive, faster, and more energy-efficient. The CPU-less, memory-mapped mode of operation of the FLS is simpler and more robust than was the CPU-based operation of the assembly of at least two CPU-based cards. The FLS is more flexible in that all logic is implemented in reprogrammable logic devices.

This work was done by Robert C. Kunz of RMS, Jason Dowling and Terry L. Graessle of Lockheed Martin, and Christos Karasiotos and David Fisher of SGT for Goddard Space Flight Center. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp  under the Electronics & Computers category. GSC-14034

NASA Tech Briefs Magazine

This article first appeared in the February, 2000 issue of NASA Tech Briefs Magazine.

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