Architectures have been proposed for the design of frequency-domain least-mean-square complex equalizers that would be integral parts of parallel-processing digital receivers of multigigahertz radio signals and other quadrature - phase - shift - keying (QPSK) or 16 - quadrature - amplitude - modulation (16-QAM) of data signals at rates of multiple gigabits per second. "Equalizers" as used here denotes receiver subsystems that compensate for distortions in the phase and frequency responses of the broad-band radio-frequency channels typically used to convey such signals. The proposed architectures are suitable for realization in very-large-scale integrated (VLSI) circuitry and, in particular, complementary metal oxide semiconductor (CMOS) application-specific integrated circuits (ASICs) operating at frequencies lower than modulation symbol rates.

Figure 1. A Parallel-Processing Digital Receiver would include a parallel-processing equalizer.

A digital receiver of the type to which the proposed architecture applies (see Figure 1) would include an analog-to-digital converter (A/D) operating at a rate, fs, of 4 samples per symbol period. To obtain the high speed necessary for sampling, the A/D and a 1:16 demultiplexer immediately following it would be constructed as GaAs integrated circuits. The parallel-processing circuitry downstream of the demultiplexer, including a demodulator followed by an equalizer, would operate at a rate of only fs/16 (in other words, at 1/4 of the symbol rate). The output from the equalizer would be four parallel streams of in-phase (I) and quadrature (Q) samples.

The proposed architectures would implement subconvolution (see Figure 2), fast - Fourier - transform/inverse - fast - Fourier - transform (FFT-IFFT), and discrete - Fourier - transform/inverse - discrete - Fourier - transform (DFT-IDFT) overlap-and-save filter algorithms. A key property of the proposed architectures is that one can make engineering compromises among computational efficiency, complexity of circuitry, and processing rates. Such trades are made possible, in part, by utilizing subconvolutions and relatively simple digital signal-processing methods in such a manner as to eliminate a lower bound imposed on FFT-IFFT lengths by equalizer tap lengths. For a given receiver, the equalizer tap length would theoretically be unlimited, and the FFT-IFFT length could be chosen completely independently of the equalizer tap length. The FFT-IFFT length could be determined on the basis of the desired reduction in the processing rate. The specific values chosen for the proposed architectures are an equalizer tap length of 32, with an FFT-IFFT length of 8 chosen to enable processing at 1/4 of the symbol rate.

This work was done by Andrew Gray, Parminder Ghuman, Scott Hoy, and Edgar H. Satorius of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at under the Electronics/Computers category.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to

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Refer to NPO-30246, volume number and page number.

This Brief includes a Technical Support Package (TSP).
Parallel-Processing Equalizers for Multi-Gbps Communications

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This article first appeared in the March, 2004 issue of NASA Tech Briefs Magazine.

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