Several improvements in the designs of flip-flop circuits that are parts of logic circuits have been proposed to reduce the incidence of logic errors associated with single- event upsets (SEUs) [bit flips caused by incident energetic ionizing particles]. Traditionally, radiation-hardened integrated circuits have been manufactured on special process lines, with emphasis, variously, on immunity to latchups and SEUs for outer-space applications or on total-dose hardness for military applications. The present improvements are intended to confer latchup and SEU immunity of a degree and type suitable for outer-space applications, but unlike in the traditional approach, the improved designs could be implemented on ordinary commercial complementary metal oxide semiconductor (CMOS) process lines.

This Compact SEU-Immune Flip-Flop Circuit would be almost completely immune to SEU. The two extra inverters together with the normal gating transistors provide three independent delay stages for absorbing glitches, the minimum theoretically required. Glitches are absorbed whether generated internally, or whether coming in on the Data or clock (GB) lines, as long as the timing guidelines are followed. What is shown is a latch, which is 1/2 of the common D-flip-flop circuit.
A complete description of the proposed improvements and of the historical back- ground prerequisite to understanding the improvements would greatly exceed the space available for this article; only a brief summary can be given here. Historically, guard rings have been used to prevent latchups. In theory, SEU can be eliminated via redundancy, but conventional redundancy involves at least 3 copies of all basic logic circuitry plus additional logic circuitry in the form of an infallible voter circuit. One patented scheme calls for dual redundant flip-flop circuits, called “Whitaker cells” after their inventor, in which what is known about the possible directions of upsets in n- and p-channel devices is utilized to enable the cells to recover from upsets. Numerous other prior developments involve using extra delays within the flip-flop to reduce its susceptibility to glitches. These include the addition of passive components, which are often expensive to fabricate in a logic process, or extra pairs of inverter stages. The minimum number of extra inverter stages described in prior art is 2 pair, or 4 extra inverters. There are also other non-Whitaker schemes involving dual flip-flops cross-coupled in some novel way to avoid or reduce upset.

In the dual flip-flop schemes, dual rail logic may be used to drive the pair of flip-flops. In the Whitaker scheme, single rail logic may also be used, with the second flip-flop data provided through a delay equal to the worst-case glitch time for the logic family, which eliminates the possibility of a glitch arriving simultaneously on both flip-flops. The worst-case time is approximately the propagation time for a fully loaded node on the slowest gate. All gates must be designed with balanced rise and fall times for this to work. Glitches on clock lines must be avoided either by distributing clock signals separately to the two sides of the dual flip-flop, or using extra capacitances (up to 4 pF) and large drivers on all clock lines, and avoiding the generation of a clock line internally. These are very restrictive and expensive constraints. Nor do these prior developments provide for asynchronous preset and clear operations.

The proposed improvements are summarized as follows:

  • Optimized transistor sizing is used to make the shortest possible delay elements in a delay-based design, without resorting to passive components or more than one extra pair of inverters within the flip-flop. This requires fewer transistors than prior delay-based designs, and far fewer than any of the dual flip-flop designs.
  • Some of the delay is distributed into existing transistors within the flip-flop in order to control the glitch times which can be generated within the flipflop, while absorbing external data or clock line glitches.
  • The same delay-based technique would be used to enable asynchronous preset and clear.
  • Only one guard ring with allowed polycrystalline-silicon crossings would be used.
  • Multistage balanced rise and fall times inside an ordinary flip-flop would be used to absorb glitches without changing state of the flip-flop.

Circuits that incorporate the proposed improvements could be simpler, more compact, and more functional, relative to prior SEU-immune circuits based on dual flip-flops or more costly delays. The delays involved, approximately one to two gate delay times in operation of the flip-flop, are comparable or less than the delays introduced in all prior forms of radiation-tolerant flip-flops (except the expensive and complicated case of dual flip-flops driven by dual-rail logic).

This work was done by Robert Shuler, Jr., of Johnson Space Center.

This invention is owned by NASA, and a patent application has been filed. Inquiries concerning nonexclusive or exclusive license for its commercial development should be addressed to

the Patent Counsel
Johnson Space Center
(281) 483-0837.

Refer to MSC-22953.


NASA Tech Briefs Magazine

This article first appeared in the August, 2002 issue of NASA Tech Briefs Magazine.

Read more articles from the archives here.