The Parallel Integrated Frame Synchronizer (PIFS) chip is one of three very-large-scale integrated (VLSI) circuits designed for ground processing of streams of telemetric data received from spacecraft. These application-specific integrated circuits (ASICs) are the main components of a developmental advanced telemetric-data-processing system that is intended to be smaller, cheaper, and more capable than its predecessors. Each of these ASICs is intended to perform most of the functions heretofore performed by multiple integrated circuits on printed-circuit cards. These ASICs are designed mainly to accommodate the packet-telemetry-data protocols recommended by the Consultative Committee for Space Data Systems (CCSDS); however, they also have generic capabilities in that they are programmable and can therefore also be made to handle telemetry in special data formats.

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Figure 1. In Comparison with Prior Frame-synchronizer Circuitry, the PIFS chip is smaller, cheaper, and more capable.
The three ASICs are used in return-link processing, which is the digital processing that takes place after the reception, demodulation, and digitization of signals transmitted from spacecraft. The return-link processing functions are apportioned sequentially among the three ASICs as follows:

  1. The PIFS chip delineates frames of data from the incoming serial bit stream by implementing a sophisticated algorithm that searches for frame synchronizers, which are prescribed bit sequences placed at the frame boundaries.
  2. The output of the PIFS chip is fed to the second ASIC, which is the Reed-Solomon Error Correction (RSEC) chip. For powerful protection against errors that can enter both the data and the protocol structures, the data frames are Reed-Solomon encoded, with interleaving, prior to transmission from the spacecraft. The RSEC decodes and de-interleaves the data and corrects any Reed-Solomon-correctable errors.
  3. The output of the RSEC chip is fed to the third ASIC, which is the CCSDS Service Processor chip. This chip demultiplexes, extracts, and validates user data from the composite stream of telemetry frames.

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Figure 2. This Block Diagram depicts the flows of data and the major data-processing functional subdivisions of the PIFS.

The PIFS chip is a complementary metal oxide/semiconductor (CMOS) gate array laid out according to 0.6-µm design rules. As its name indicates, the PIFS chip implements a parallel-processing algorithm for synchronization of telemetry frames. Parallel processing requires logic circuitry significantly more complex than that required for serial processing; however, because advances in VLSI have greatly reduced the costs and sizes of logic circuits, the greater complexity of the PIFS design is no longer a disadvantage. As shown in Figure 1, the PIFS chip is much smaller than two older multiple-VLSI-chip serial-processing frame synchronizers that it is intended to replace.

The PIFS chip is controlled by a set of internal registers that are configured through a standard microprocessor interface (see Figure 2) prior to operation. The registers afford the programmability that enables the PIFS to satisfy the frame-synchronization requirements of many different spacecraft missions. During operation, data enter the chip in one of two ways:

  • If the data rate is very high, the serial data stream is first externally converted to a byte-wide parallel data stream and then fed into an internal first-in/first-out (FIFO) memory.
  • If the data rate is

The FIFO memory enables the logic circuitry within the PIFS to be synchronized with a separate master clock; this feature, in combination with a data-flow architecture, offers several advantages over older frame synchronizers, including lower latency, easier processing of nested or asynchronously blocked data, and automatic pipeline flushing. As data pass through the chip, correlations are computed, locations of synchronizers are calculated, and data are aligned to frame boundaries. The PIFS chip performs a superset of the functions of prior frame synchronizers, including cumulative quality accounting, time stamping, real-time quality trailer generation, and capability to synchronize all current weather-satellite formats. One exception is reverse data handling, which is expected to become unnecessary because of the planned ubiquitous use of solid-state recorders aboard spacecraft.

This work was done by Parminder S. Ghuman and Toby Bennett of Goddard Space Flight Center and Jeff Solomon formerly of RMS Technologies. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp under the Electronics & Computers category.

This invention is owned by NASA, and a patent application has been filed. Inquiries concerning nonexclusive or exclusive license for its commercial development should be addressed to

the Patent Counsel
Goddard Space Flight Center; (301) 286-7351.

Refer to GSC-13813.