An architecture for a proposed active pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic-vision and general pointing and tracking applications.
CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or lownoise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications.
The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 µm. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 × 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each.
A typical prior CMOS APS operates in a row-at-a-time (“rolling-shutter”) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/read-later mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The diagonal-switch and memory addresses would be generated by the on-chip controller.
The memory array would be large enough to hold differential signals acquired from all 8 windows during a frame period. Following the rapid sampling from all the windows, the contents of the memory array would be read out sequentially by use of a capacitive transimpedance amplifier (CTIA) at a maximum data rate of 10 MHz. This data rate is compatible with an update rate of almost 10 Hz, even in full-frame operation. In the multiwindow readout mode, this APS could operate with ultralow noise. When an APS of prior design is operated in row-at-a-time readout, the main component of noise in each pixel is the reset noise at the sensing node. In the proposed APS, the reset levels for an entire frame would be stored in the memory array, and subsequently used as references during differential readout; that is, for each pixel, its own reset level would be subtracted from its signal. In other words, this APS would perform on-chip correlated double sampling, eliminating sensing-node reset noise. Hence, the remaining main component of readout noise from each pixel would be that associated with sampling of the signal and reset levels into the memory array. It has been estimated that using a sampling capacitance of 2 pF (corresponding to a root-mean-square differential sampling noise of ≈65 µV) and a nominal pixel conversion gain of 15 µV per electron, the readout noise would be less than 5 electrons. In full-frame operation, the APS imager would revert to the row-ata- time readout mode, with a consequent increase in readout noise to 30 electrons.
This work was done by Bedabrata Pain, Chao Sun, Guang Yang, and Julie Heynssens of Caltech for NASA’s Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Electronics/ Computers category. In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to: Innovative Technology Assets Management:
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