A recently developed high-speed digital correlator is especially well suited for processing readings of a passive microwave polarimeter. This circuit computes the auto-correlations of, and the cross-correlations among, data in four digital input streams representing samples of in-phase (I) and quadrature (Q) components of two inter-mediate-frequency (IF) signals, denoted A and B, that are generated in heterodyne reception of two microwave signals. The IF signals arriving at the correlator input terminals have been digitized to three levels (-1,0,1) at a sampling rate up to 500 MHz. Two bits (representing sign and magnitude) are needed to represent the instantaneous datum in each input channel; hence, eight bits are needed to represent the four input signals during any given cycle of the sampling clock. The accumulation (integration) time for the correlation is programmable in increments of 2 8 cycles of the sampling clock, up to a maximum of 2 24 cycles.
The basic functionality of the correlator is embodied in 16 correlation slices, each of which contains identical logic circuits and counters (see figure). The first stage of each correlation slice is a logic gate that computes one of the desired correlations (for example, the autocorrelation of the I component of A or the negative of the cross-correlation of the I component of A and the Q component of B). The sampling of the output of the logic gate output is controlled by the sampling-clock signal, and an 8-bit counter increments in every clock cycle when the logic gate generates output. The most significant bit of the 8-bit counter is sampled by a 16-bit counter with a clock signal at 2 -8 the frequency of the sampling clock. The 16-bit counter is incremented every time the 8-bit counter rolls over. The correlator is designed for use with a microprocessor. The microprocessor controls the function of the correlator, sets the desired integration time by writing appropriate values to registers in the correlator, and reads the correlation outputs as described next. At the end of the integration period, the contents of the 16-bit counter are copied to a 16-bit buffer, and the 16-bit counter is cleared to begin a new accumulation cycle. At the same time, the correlator generates a signal to indicate, to the microprocessor, that new correlation data are available. The correlator and the microprocessor communicate via a simple 3.3-V bus-oriented interface, such that from the perspective of the microprocessor, the correlator acts much like a small random-access memory containing 32 16-bit words. Hence, the microprocessor reads the correlation-slice buffers by supplying five-bit addresses to select the buffers as a group of memory locations. The correlator has been implemented as a complementary metal oxide/semiconductor (CMOS) integrated circuit, following 0.35-µm radiation tolerant design rules. The main advantage of this high-speed digital correlator over prior ones is ultralow-power dissipation: whereas a previous high-speed digital correlator dissipates a power of about 10 W (and processes only two input data COTS streams), this correlator dissipates a power of 2 mW or less, the exact value depending on the sampling rate. To achieve such ultralow-power operation a logic level of only 0.5 V is used, necessitating the use of special signal-conditioning circuits.
This work was done by Jeffrey R. Piepmeier of Goddard Space Flight Center and K. Joseph Hass of the University of Idaho. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Electronics/Computers category. GSC-14746-1