The synthesis of some fuzzy-logic circuits by use of evolvable hardware (EHW) has been demonstrated in an investigation of EHW as a means of auto- mated synthesis of computational-intelligence circuitry in general. This investigation is, in turn, part of continuing research on the broader topic of EHW as the basis of a general method of automated design and/or automated direct synthesis of electronic circuits that can perform acceptably close approximations of any desired analog and/or digital functions.
The basic concepts and some specific implementations of EHW were described in several previous NASA Tech Briefs articles, namely: “Reconfigurable Arrays of Transistors for Evolvable Hardware” (NPO-20078), Vol. 25, No. 2 (February 2001), page 36; “Evolutionary Automated Synthesis of Electronic Circuits” (NPO-20535), Vol. 26, No. 7 (July 2002), page 33; “Designing Reconfigurable Antennas Through Hardware Evolution” (NPO-20666), Vol. 26, No. 7 (July 2002), page 34; “‘Morphing’ in Evolutionary Synthesis of Electronic Circuits” (NPO-20837), Vol. 26, No. 8 (August 2002), page 31; and “Mixtrinsic Evolutionary Synthesis of Electronic Circuits” (NPO-20773), Vol. 26, No. 8 (August 2002), page 32.
To recapitulate from the cited prior articles: “Evolution” and “evolvable” as applied to EHW are meant in a quasi-genetic sense, referring to the construction and testing of a sequence of populations of circuits that function as incrementally better solutions of a given design problem. Evolution is effected through the selective, repetitive connection and/or disconnection of transistors, amplifiers, inverters, and/or other circuit building blocks. The evolution is guided by a search-and-optimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits the desired behavior. If evolved circuits are tested by mathematical modeling (that is, computational simulation) only, the evolution is said to be extrinsic; if they are tested in real hardware, the evolution is said to be intrinsic; if they are tested in random sequences of computational simulation and real hardware, the evolution is said to be mixtrinsic.
For the synthesis of fuzzy-logic circuitry following the present approach, the hardware portion of an EHW system is a field-programmable transistor array (FPTA) — a very-large-scale integrated (VLSI) circuit that contains electronically reconfigurable cellular arrays of transistors (optionally also including resistors and capacitors). “Electronically reconfigurable” signifies that the electrical connections among elements of an array are made and broken by use of transistor switches that are commanded to open or close, respectively, by control bit strings generated by an evolutionary algorithm. EHW is especially attractive as a potential means of synthesizing combinatorial fuzzy-logic circuits because it is very difficult to synthesize such circuits by conventional design methods. When fuzzy logic is implemented in electronically reconfigurable circuitry, there is an additional advantage of flexibility to change the circuitry in the event that a need for changed fuzzy logic arises during operation.
The fuzzy-logic operators considered thus far in the investigation are of a subtype of the type known in the art as triangular norms and conorms. The triangular norms and conorms are used in fuzzy logic to represent conjunctions (roughly the equivalent of AND operators) and disjunctions (roughly the equivalent of OR operators). A triangular norm or conorm of the particular subtype considered is a function of two input signals (x and y) and a parameter (s). In the case s = 0, this particular triangular norm or conorm is a minimum or maximum function (equal to x or y, which is smaller or larger, respectively); in cases of s ≠ 0, this triangular norm and conorm are more complex functions of x and y. The figure depicts the response of a circuit that was evolved directly in hardware on a FPTA chip for the case s = 100, for which the triangular norm is given by
This work was done by Adrian Stoica of Caltech for NASA’s Jet Propulsion Laboratory.
Refer to NPO-21095.