Analog electronic circuits that operate with pulsed input and output signals are undergoing development. The pulsing behavior of these circuits is modeled after a similar behavior, called "spiking," that occurs in biological neural networks. In these circuits, the pulse times and/or the pulse-repetition rates can convey information. These circuits are intended especially for use in high-speed artificial neural networks, which, like the brains of animals that have vision, would process image data to effect invariant pattern recognition. (As used here, "invariant"signifies that the ability to recognize patterns would not be adversely affected by such effects as translation, rotation, distortion, changes in scale, or changes in brightness.)

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Figure 1. The Interval Between Spikes and the Buildup of Membrane Potential can be modulated by modulating the threshold potential.
Figure 1 depicts an example of input/output behavior according to one mathematical model of a biomorphic spiking neuron. Starting from the beginning of a pulse cycle, a membrane potential rises at rate that decays exponentially until the potential passes a time-varying threshold, at which point the neuron sends a spike along its axon. At the instant of the spike, the membrane potential returns to a resting level from which the cycle starts anew. If the threshold, the resting potential, or the rate of rise of the membrane potential is modulated, then the pulse-repetition rate (also called the "spiking frequency" or the "firing rate") of the neuron is changed.

By locally connecting neurons like this one into an array in which the axons of neighbors would transmit their spike trains via synapto-dendritic connections that would modulate the thresholds, one could construct a complex processing network. In a computational simulation, such a network has been shown to be capable of invariant mapping of binary patterns.

The invariance of the mapping is a result of encoding images in time rather than space. In particular, if the same image is fed as input to a different set of pixels but the same spatial relationships are maintained among parts of the image, the temporal representation of the image remains the same and the mapping is invariant to translation. Invariance with respect to brightness is achieved partly by recognizing that greater brightness is represented simply by a uniform increase in the average firing rates of all affected neurons.

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Figure 2. These Analog Neural Circuits are designed to exhibit spiking behavior that approximates that of figure 1.
The upper part of Figure 2 depicts a developmental spiking-neuron circuit. The clock voltage source (Vclk) pumps charge through a subthreshold biased transistor (M1) onto the gate capacitance of transistor M2, the gate potential of which represents the membrane potential. The current source constituted by the clock and M1 is intentionally made fairly poor (i.e., is made to have low resistance) in order to obtain a nonlinear buildup of membrane potential. When the membrane potential becomes high enough to pull M3 out of its linear current-vs.-voltage region, the voltage at the swing node rapidly decreases as M2 pulls the node toward ground. The low voltage on the swing node then triggers the inverter formed with M4 and M5 to go high, and the inverter potential is digitally buffered to the output terminal. The clocked switching transistor M7 latches the voltage output on the noncharging portion of the cycle of the current pump at M1. M8 and M9 are sized to constitute an inverter that triggers at a relatively high dc potential to insure an adequate spike amplitude before the discharge transistor M6 is activated. When M6 is switched on, all charge at the membrane is drained to ground (zero potential) or, alternatively, to a source of nonzero resting potential connected to the source terminal of M6. When the membrane potential falls, M2 shuts down and the swing node is pulled high again as M3 returns to its linear region. This change in the swing node returns the output to low, ending the spike and switching off the discharge transistor at M6.