This innovation is used to connect between synapse and neuron arrays using nanowire in quantum dot and metal in CMOS (complementary metal oxide semi-conductor) technology to enable the density of a brainlike connection in hardware. The hardware implementation combines three technologies:
- Quantum dot and nanowire-based compact synaptic cell (50×50 nm2) with inherently low parasitic capacitance (hence, low dynamic power ≈10–11 watts/synapse),
- Neuron and learning circuits implemented in 50-nm CMOS technology, to be integrated with quantum dot and nanowire synapse, and
- 3D stacking approach to achieve the overall numbers of high density O(1012) synapses and O(108) neurons in the overall system.
In a 1-cm2 of quantum dot layer sitting on a 50-nm CMOS layer, innovators were able to pack a 106-neuron and 1010-synapse array; however, the constraint for the connection scheme is that each neuron will receive a non-identical 104-synapse set, including itself, via its efficacy of the connection.
This is not a fully connected system where the 100×100 synapse array only has a 100-input data bus and 100-output data bus. Due to the data bus sharing, it poses a great challenge to have a complete connected system, and its constraint within the quantum dot and silicon wafer layer.
For an effective connection scheme, there are three conditions to be met:
- Local connection.
- The nanowire should be connected locally, not globally from which it helps to maximize the data flow by sharing the same wire space location.
- Each synapse can have an alternate summation line if needed (this option is doable based on the simple mask creation).
The 103×103-neuron array was partitioned into a 10-block,102×103-neuron array. This building block can be completely mapped within itself (10,000 synapses to a neuron).
This work was done by Tuan A. Duong, Christopher Assad, and Anilkumar P. Thakoor of Caltech for NASA’s Jet Propulsion Laboratory.