A proposed integrated circuit based on quantum-dot cellular automata (QCA) would function as a bit-serial adder. This circuit would serve as a prototype building block for demonstrating the feasibility of quantum-dots computing and for the further development of increasingly complex and increasingly capable quantum-dots computing circuits. QCA-based bit-serial adders would be especially useful in that they would enable the development of highly parallel and systolic processors for implementing fast Fourier, cosine, Hartley, and wavelet transforms.
The proposed circuit would complement the QCA-based circuits described in "Implementing Permutation Matrices by Use of Quantum Dots" (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42, and the preceding article. Those articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCA-based signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.
To enable a meaningful description of the proposed bit-serial adder, it is necessary to further recapitulate the description of a quantum-dot cellular automation from the first-mentioned prior article: A quantum-dot cellular automaton contains four quantum dots positioned at the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantum-mechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns.
Again, for reasons too complex to describe here, in order to ensure accuracy and timeliness of the output of a QCA array, it is necessary to resort to an adiabatic switching scheme in which the QCA array is divided into subarrays, each controlled by a different phase of a multiphase clock signal. In this scheme, each subarray is given time to perform its computation, then its state is frozen by raising its interdot potential barriers and its output is fed as the input to the successor subarray. The successor subarray is kept in an unpolarized state so it does not influence the calculation of preceding subarray. Such a clocking scheme is consistent with pipeline computation in the sense that each different subarray can perform a different part of an overall computation. In other words, QCA arrays are inherently suitable for pipeline and, moreover, systolic computations. This sequential or pipeline aspect of QCA would be utilized in the proposed bit-serial adders.
The design of the proposed bit-serial adder incorporates a two-step innovation: (1) the design of an efficient QCA-based circuit that would function as a full adder, and (2) the design of QCA-based feedback loop with proper clocking that would enable the full adder to perform bit-serial addition. The full adder (see Figure 1) would contain three inverter gates and five majority gates. Given two input bits (A and B) and one previous carry bit (Ci–1), this circuit would generate a sum bit (S) and a new carry bit (Ci).
A bit-serial adder would perform the addition operation on two sequences of input bits (ai and bi for i = 1 to n) to generate a sequence of sum bits (Si for i = 1 to n + 1). To be able to perform the addition operation, the adder would have to be capable of storing the intermediate carry bits. A feedback loop could be used to effect such storage.
Figure 2 schematically depicts a bit-serial adder containing three majority gates and two inverter gates. This circuit could, optionally, be used as a full adder, in which role it would be more efficient, relative to the adder of Figure 1, in that it would contain fewer gates. The main advantage of the circuit of Figure 2 is that by use of suitable multiphase clocking, one could cause part of the circuit to act as a feedback loop for temporary storage of intermediate carry bits, thus enabling bit-serial addition. The ability of this circuit to perform bit-serial addition has been verified by computer simulation. However, several obstacles to practical implementation of a QCA-based bit-serial adder that could function without error at room temperature must still be overcome.
This work was done by Amir Fijany, Nikzad Toomarian, Katayoon Modarress, and Matthew Spotnitz of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Computers/Electronics category. NPO-20869.
This Brief includes a Technical Support Package (TSP).
Bit-Serial Adder Based on Quantum Dots
(reference NPO-20869) is currently available for download from the TSP library.
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