Metal oxide semiconductor (MOS) circuits for measuring spatially varying intensities of beams of low-energy charged particles have been developed. These circuits are intended especially for use in measuring fluxes of ions with spatial resolution along the focal planes of mass spectrometers. Unlike prior mass-spectrometer focal-plane detectors, these MOS circuits would not be based on ion-induced generation of electrons, and photons; instead, they would be based on direct detection of the electric charges of the ions. Hence, there would be no need for microchannel plates (for ion-to-electron conversion), phosphors (for electron-to-photon conversion), and photodetectors (for final detection) — components that degrade spatial resolution and contribute to complexity and size.

The developmental circuits are based on linear arrays of charge-coupled devices (CCDs) with associated readout circuitry (see figure). They resemble linear CCD photodetector arrays, except that instead of a photodetector, each pixel contains a capacitive charge sensor. The capacitor in each sensor comprises two electrodes (typically made of aluminum) separated by a layer of insulating material. The exposed electrode captures ions and accumulates their electric charges during signal-integration periods.

The CCD array is of a standard three-phase type. The array circuitry includes a shift register and a charge-mode input structure denoted a "fill-and-spill" structure. This structure provides the coupling through which the charge accumulated in each capacitive sensor gives rise to a packet of signal charge in the shift register. The fill-and-spill structure has previously been shown to keep the nonlinear component of response below —100 dB, with negligible offset. An ancillary benefit of the fill-and-spill design is elimination of a noise component proportional to

kTC (where k is Boltzmann's constant, T is absolute temperature, and C is capacitance) that would be present if the charge-storage wells in the array were to be filled via diode sources. By appropriate design, the fill-and-spill structure can be made to provide gain in the charge domain. The design under consideration at the time of reporting the information for this article is expected to provide a gain of 10.

The signal charges are clocked through the shift register in basically the same manner as that of a CCD photodetector array. After clocking through the array, the signal charge is presented to a charge-to-voltage-conversion output amplifier. Unlike in some CMOS photodetector circuits, there is only one such amplifier. This feature minimizes variations of signal gain and signal offset among pixels.

ImageA Linear CCD Array contains capacitive charge sensors (instead of photodetectors) in the detector areas. Four representative pixels of the array are shown here. The detector array has many pixels (e.g., 1,024 pixels for 25-mm long array).

This work was done by Mahadeva Sinha and Mark Wadsworth of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp under the Computers/Electronics category.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to

Intellectual Property group

JPL

Mail Stop 202-233

4800 Oak Grove Drive

Pasadena, CA 91109

(818) 354-2240

Refer to NPO-21168, volume and number of this NASA Tech Briefs issue, and the page number.