A custom high-speed charge-coupled-device (CCD) camera that features a capability for real-time readout from multiple regions of interest (subwindows) within its field of view is undergoing development. The camera was designed initially as a means of tracking a remote laser beacon in a free-space optical communication system. The basic camera design is also adaptable to eye-tracking, target-tracking, and machine-vision systems.

The figure depicts the camera as installed in a laboratory test bed. The camera includes a 658 x 496-pixel commercial CCD integrated-circuit chip capable of subwindow readout. The CCD chip is mounted on a circuit card, denoted the CCD imager card. Also mounted on the imager card are (1) level-translator and buffer circuitry for the CCD strobe lines and (2) a pair of commercial analog signal-processor chips, each of which performs correlated double sampling, includes a 10-bit analog-to-digital converter, and accommodates serial programming for setting amplifier gain, pixel bias level, and other operational parameters.

This Block Diagram shows the camera as installed in a test bed built previously for demonstrating acquisition and tracking of a laser beacon for a free-space optical communication system.
A digital signal processor (DSP), mounted on another card, is used to issue commands to, and read images from, the camera. Still another circuit card, denoted the focal-plane-array (FPA) interface card, contains a pair of field-programmable gate arrays that serve as part of an interface between the circuitry on the CCD imager card and the DSP. The rest of the CCD-imager/DSP interface comprises a global bus and custom bus interface logic circuitry, which implements the logic for an address decoder, a handshake mechanism, and data-path buffers for access to the camera via the global bus port of the DSP.

Preliminary test data suggests that it is possible to achieve a frame rate of 6 kHz for 8 x 8-pixel subwindows with a pixel resolution and dynamic range of 7 bits. Planned refinements in camera and test bed are expected to increase the frame rate in the fastest area of the CCD to 17 kHz and the pixel resolution to 10 bits.

This work was done by Steve Monacos and Angel Portillo of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp under the Electronic Components and Systems category.

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