A methodology and software to implement the methodology are under development in an effort to automate at least part of the process of designing integrated-circuit (IC) chips that perform complex data-processing fun- ctions. An important element of the methodology is reuse of prior designs, with modifications as required to optimize for a specific application. This minimizes a labor-intensive, errorprone part of the design process. The prior designs include what are known in the art as intellectual-property (IP) cores — that is, designs of functional blocks [e.g., random-access memories (RAMs), communications circuits, processors] that are incorporated into larger designs. Circuits may be optimized with respect to design goals, such as reducing chip size, reducing power consumption, and/or increasing radiation hardness.
The methodology is implemented by an extensible computer program denoted Kompiler (not to be confused with an identically named artificial-intelligence program mentioned in the computer literature dating back at least as far as 1955). Kompiler (see figure) affords capabilities for writing customized code in very- high-speed integrated-circuit (VHSIC) hardware description language (VHDL), with generation of test vectors, execution of synthesis, and simulation for verification. Generation of VHDL code for a functional block is performed by utilizing a previously coded generic software equivalent of a template (e.g., an IP core), the contents of which are embedded in the source code of Kompiler.
Kompiler provides a user interface that enables selection of various options to satisfy the requirements of the particular application in which the functional block is intended to be used, while enabling a tradeoff between resources and features. For designing a read-only memory (ROM) or data-heavy component, input data are provided in the form of a specially formatted ASCII text file. Kompiler also affords options for selection of synthesis software and for choosing among coding styles, as coding styles can strongly affect the results of the logic synthesis. By use of these features of Kompiler, one can generate a customized version of the VHDL code of a generic functional block.
One of the initial applications and a complex test case for the Kompiler concept is the redesign of a commercial single- chip FPGA (field-programmable gate array) controller, denoted the AM29CPL154, that is radiation-soft, consumes high power by present standards, and is no longer manufactured. The redesigned version, denoted the 29KPL154, is intended to be radiationhard, less power-hungry, and smaller, yet able to perform all the functions of the prior commercial version.
This work was done by Richard Katz of Goddard Space Flight Center and Igor Kleyner. For more information, contact the Goddard Commercial Technology Office at 301-286-5810.