Two algorithms have been conceived to enable automated, thorough testing of Built-in test (BIT) software. The first algorithm applies to BIT routines that define pass/fail criteria based on values of data read from such hardware devices as memories, input ports, or registers. This algorithm simulates effects of errors in a device under test by (1) intercepting data from the device and (2) performing AND operations between the data and the data mask specific to the device. This operation yields values not expected by the BIT routine. This algorithm entails very small, permanent instrumentation of the software under test (SUT) for performing the AND operations.

The second algorithm applies to BIT programs that provide services to users’ application programs via commands or callable interfaces and requires a capability for test-driver software to read and write the memory used in execution of the SUT. This algorithm identifies all SUT code execution addresses where errors are to be injected, then temporarily replaces the code at those addresses with small test code sequences to inject latent severe errors, then determines whether, as desired, the SUT detects the errors and recovers.

This work was done by Thomas K. Gender and James Chow of Honeywell, Inc., for Johnson Space Center.

Title to this invention has been waived under the provisions of the National Aeronautics and Space Act {42 U.S.C. 2457(f)}, to Honeywell, Inc. Inquiries concerning licenses for its commercial development should be addressed to:

Satellite Systems Operation
Honeywell, Inc.
P.O. Box 52199
Phoenix, AZ 85072-2199

Refer to MSC-23463-1/4-1, volume and number of this NASA Tech Briefs issue, and the page number.

NASA Tech Briefs Magazine

This article first appeared in the August, 2010 issue of NASA Tech Briefs Magazine.

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