High-aspect-ratio silicon structures are necessary components in many MEMS (microelectromechanical systems). Aspect ratio is defined as the ratio of the height of the structure to its lateral width. The structures are typically fabricated through bulk micromachining steps such as deep reactive ion etching. In some cases, multiple levels of high-aspect-ratio structures are required. For instance, one may want to etch completely through a silicon wafer to thermally isolate a bolometer or provide waveguide coupling to an antenna defined on an insulating membrane, and at the same time have integrated high-topology structures required for microwave coupling or filtering. Definition of the structures typically uses photolithographic technology. But for high-aspect-ratio structures, spin cast resist becomes difficult to incorporate due to the non-uniform thickness of the resist around tall structures. One can cast very thick layers of photoresist, but this limits the minimum feature size, and additionally, very thick layers of photoresist are difficult to work with due to solvent release and moisture that can cause the resist to crack or swell. For electromagnetic reasons, the structures would preferably be made from conductive material such as metal or degeneratively doped silicon. The objective of this work was to incorporate multiple levels of conductive high-aspectratio structures with standard micromachining processes.

The new microfabrication technology incorporates multiple levels of high-aspectratio structures into a single piece of silicon. The technology can be used to incorporate photonic waveguide joints with through wafer-etched structures. The process starts with a silicon wafer that may have completed microwave or other device processing. In the case where a conductive layer is required, the silicon may be degeneratively doped. A layer of metal is deposited and patterned by standard processes. The metal may be used as a wirebond contact or to improve thermal and electromagnetic coupling. Next, a layer of photoresist is spin cast at the desired thickness of approximately 12 μm so that it will protect the silicon wafer during subsequent processing steps, such as etching completely through a 500-μm thick wafer.

The photoresist is then partially exposed through a photomask. Then, a different photomask is used to fully expose the resist. The photoresist is developed for the time required to completely remove the fully exposed photoresist in those areas where etching of the silicon is required. In the remaining areas where the photoresist was partially exposed, the photoresist absorption is such that only the surface of the photoresist has received enough UV dose to cause the resist to become soluble in developer. Therefore, photoresist will remain in those areas after development.

In the next step, the silicon is etched by deep reactive ion etching. Then, the photoresist is etched in an oxygen plasma such that the first level of resist is removed, exposing the silicon in those areas where the second level of topography is required. The silicon wafer is further etched. In this case, the original silicon layer is also etched. By stopping the first silicon etch at the correct depth, the second etch can be optimized such that two or more layers can be completed at the same time. It should be pointed out that often with a through wafer etch, an etch stop layer is incorporated with a very low etching rate. This simplifies balancing the rates between the two structures, and allows optimization of the depth of the second structure with minimal effect on the first. The process has been demonstrated for building silicon microwave backshorts with integrated photonic choke structures.

This work was done by Kevin Denis of Goddard Space Flight Center. For more information, contact the GSFC Technology Transfer Office at (301) 286-5810 or This email address is being protected from spambots. You need JavaScript enabled to view it.. Refer to GSC-16931-1.

NASA Tech Briefs Magazine

This article first appeared in the April, 2016 issue of NASA Tech Briefs Magazine.

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