A family of experimental highly miniaturized field-effect transistors (FETs) is based on exploitation of the electrical properties of nanofibers of polyaniline/ polyethylene oxide (PANi/PEO) doped with camphorsulfonic acid. These polymer-based FETs have the potential for becoming building blocks of relatively inexpensive, low-voltage, high-speed logic circuits that could supplant complementary metal oxide/semiconductor (CMOS) logic circuits.

The development of these polymerbased FETs offers advantages over the competing development of FETs based on carbon nanotubes. Whereas it is difficult to control the molecular structures and, hence, the electrical properties of carbon nanotubes, it is easy to tailor the electrical properties of these polymerbased FETs, throughout the range from insulating through semiconducting to metallic, through choices of doping levels and chemical manipulation of polymer side chains. A further advantage of doped PANi/PEO nanofibers is that they can be made to draw very small currents and operate at low voltage levels, and thus are promising for applications in which there are requirements to use many FETs to obtain large computational capabilities while minimizing power demands.

ImageFabrication of an experimental FET in this family begins with the preparation of a substrate as follows: A layer of silicon dioxide between 50 and 200 nm thick is deposited on a highly doped (resistivity ≈0.01 Ω·cm) silicon substrate, then gold electrodes/contact stripes are deposited on the oxide. Next, one or more fibers of camphorsulphonic acid-doped PANi/ PEO having diameters of the order of 100 nm are electrospun onto the substrate so as to span the gap between the gold electrodes (see Figure 1).

ImageFigure 2 depicts measured current versus voltage characteristics of the device of Figure 1, showing that saturation channel currents occur at source to drain potentials that are surprisingly low, relative to those of CMOS FETs. The hole mobility in the depletion regime in this transistor was found to be 1.4 x 10-4 cm2/(V·s), while the one-dimensional charge density at zero gate bias was estimated to be approximately one hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (≈10-3 S/cm). Reducing or eliminating the PEO content of the fibers is expected to enhance the properties of future versions of this transistor.

This work was done by Noulie Theofylaktos, Daryl Robinson, and F¨¦lix Miranda of Glenn Research Center; Nicholas Pinto of the University of Puerto Rico; Alan Johnson, Jr. and Alan MacDiarmid of the University of Pennsylvania; and Carl Mueller of Analex Corp. For further information, access the Technical Support Package (TSP) free online at www.techbriefs.com/tsp under the Semiconductors & ICs category.

Inquiries concerning rights for the commercial use of this invention should be addressed to NASA Glenn Research Center, Innovative Partnerships Office, Attn: Steve Fedor, Mail Stop 4-8, 21000 Brookpark Road, Cleveland, Ohio 44135. Refer to LEW- 17933-1.

NASA Tech Briefs Magazine

This article first appeared in the June, 2006 issue of NASA Tech Briefs Magazine.

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