Before a new high-power semiconductor device can be used for industrial applications, it must be thoroughly tested to determine if it will survive environmental stresses and continue to meet specifications. This is especially true for the latest wide-bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) to ensure they can withstand high voltage and temperatures.

Figure 1 Single device connections for VDS ramp testing.

New application areas often mean that devices must be able to withstand severe ambient conditions. For example, in automotive traction control systems, the cooling liquid for the combustion engine may reach temperatures as high as 120 °C. To provide sufficient margin, the maximum junction temperature (TJMAX) must be increased to around 150 to 175 °C. And in safety-critical applications such as aircraft, the concept of zero-defects is being adopted to help meet stricter reliability requirements.

The VDS ramp and the High Temperature Reverse Bias (HTRB) tests are among the most common tests for evaluating the reliability of these power devices under a range of conditions.

In a VDS ramp test, drain-source voltage is stepped or ramped up from a low voltage to a voltage that's higher than the rated maximum drain-source voltage, and specified device parameters are evaluated. This test is useful for tuning design and process conditions, as well as verifying that the device delivers the expected performance. For example, dynamic RDS(ON), monitored using a VDS ramp test, provides a measurement of how much a device's ON-resistance increases after being subjected to a drain bias, while Vb or max V rating is performed when the device is OFF and drain voltage is ramped up. The VDS ramp test is generally used as a quick form of parametric verification.

An HTRB test, on the other hand, evaluates long-term stability under high drain-source bias. During an HTRB test, device samples are stressed at or slightly less than the maximum rated reverse breakdown voltage at an ambient temperature close to their maximum TJMAX over a long time — typically 1,000 hours. In HTRB testing, the leakage current is continuously monitored throughout the test and a fairly constant leakage current is generally required to pass the test. Because it combines electrical and thermal stress, this test can be used to check junction integrity, crystal defects, and ionic contamination level, which can reveal weaknesses or degradation effects in the field depletion structures at the device edges and in the passivation.

Power device characterization and reliability testing require test instrumentation with both high-voltage-sensitive current measurement capabilities. During operation, devices undergo both electrical and thermal stress. When in the ON state, they must pass tens or hundreds of amps with minimal loss (low voltage, high current). When they are OFF, they must block thousands of volts with minimal leakage currents (high voltage, low current). Additionally, during the switching transient, they are subjected to a brief period of both high voltage and high current. The high current experienced during the ON state generates a large amount of heat, which may degrade device reliability if it is not dissipated efficiently.

Factors for Successful Testing

Reliability tests typically involve high voltages, long test times, and often multiple devices under test such as for wafer level testing. This means that well-designed test systems and measurement plans are essential to avoid breaking devices, damaging equipment, and losing test data. Here are some factors to consider for successful VDS ramp and HTRB reliability testing.

Device connections — When testing vertical devices with a common drain, proper connections between the device and the test instrumentation — typically one or more source measure units (SMU) with central software control — are required to prevent stress termination in case of a single device breakdown test. As show in Figure 1a, when testing a single device, voltage can be applied at the drain only for VDS stress and measure, which requires only one SMU per device. Alternatively, as shown in Figure 1b, each gate and source can be connected to a SMU for more control for measuring current at all terminals, extending the range of VDS stress, and setting voltage on the gate to simulate a practical circuit situation. Note that final or functional testing of packaged parts is simpler compared to testing on the wafer.

Current limit control — Current limits are needed to allow for adjustment at breakdown to avoid damage to the probe card and device. When a breakdown occurs, it's advisable to keep a high-level limit current from running to that particular device because, over an extended time, the high-level current can actually melt the probe card tips and damage the devices. Therefore, reliability test solutions should include dynamic limit change functionality that allows the current limit to vary by pre-determined settings. The limit value is often set as a multiple of the measured current, and in some cases, the current should be reduced by three orders of magnitude, which corresponds to 106 times lower in terms of power.

Stress control — High-voltage stress must be well controlled to avoid over-stressing the device, which can potentially lead to unexpected device breakdown. In addition, it should be possible for the user to terminate the test early without the risk of losing already acquired data. A soft bias/abort function allows forced voltage or current to reach the desired value by ramping gradually at the start or the end of the stress, or when aborting the test, instead of changing suddenly.

Data management — Effective data collection is essential to accommodate the large datasets due to the long times involved and multi-device testing. One way to keep data volumes under control is to only log data that is important to the task at hand. For instance, data points may only be logged when a current shift exceeds a specified percentage as compared to previously logged data, or when the current is higher than a specified noise level.

The VDS ramp and HTRB tests are important power device reliability tools for parametric verification and long-term stability evaluation of the latest high-voltage power semiconductors. Software with support for the considerations outlined here, combined with precision instrumentation, can be used for a wide variety of applications at the device, wafer, or cassette level, and in settings from a simple benchtop test setup to an automated, integrated rack of instruments.

This article was written by Jennifer Cheney, Product Marketing Engineer at Tektronix, Beaverton, OR. For more information, visit