As automotive electronic systems become increasingly complex, the potential impact on the safety of the vehicle’s occupants and bystanders becomes a critical consideration. As per ISO 26262 guidelines, two classes of safety failures need to be addressed for hardware development of IPs and SoCs:
- Systematic faults, which are incorrect implementation of the safety design functionality
- Random faults, which are hardware failures that occur over time during operation
State-of-the-art functional verification techniques and flows are required to avoid systematic faults, while a safety architecture with safety mechanisms is required to monitor and detect the occurrence of random faults. The random faults analysis process starts with FMEA (Failure Mode and Effect Analysis) and continues to FMEDA (Failure Mode Effect Diagnostic Analysis) for estimating the ISO 26262 metric for SPFM (Single Point Fault Metric), LFM (Latent Fault Metric), and PMHF (Probabilistic Metric for [Random] Hardware Failures).
This 30-minute Webinar reviews the latest methodologies and technologies to efficiently and successfully achieve the functional safety verification targets for semiconductor designs.
An audience Q&A follows the technical presentation.