Semiconductors & ICs

Multiple Embedded Processors for Fault-Tolerant Computing

A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors.

Posted in: Briefs, TSP, Semiconductors & ICs, Architecture, Integrated circuits, Architecture, Integrated circuits, Semiconductors, Reliability, Reliability

Apparatus for Precise Indium-Bump Bonding of Microchips

An improved apparatus has been designed and built for use in precise positioning and pressing of a microchip onto a substrate (which could, optionally, be another microchip) for the purpose of indium-bump bonding. The apparatus (see figure) includes the following:

Posted in: Briefs, TSP, Semiconductors & ICs, Fabrication, Joining, Manufacturing equipment and machinery, Semiconductors

Flexible, Carbon-Based Ohmic Contacts for Organic Transistors

A low-temperature process for fabricating flexible, ohmic contacts for use in organic thin-film transistors (OTFTs) has been developed. Typical drainsource contact materials used previously for OTFTs include (1) vacuum deposited noble metal contacts and (2) solution deposited intrinsically conducting molecular or polymeric contacts. Both of these approaches, however, have serious drawbacks.

Posted in: Briefs, TSP, Semiconductors & ICs, Transistors, Transistors, Fabrication, Metals

Faster Evolution of More Multifunctional Logic Circuits

A modification in a method of automated evolutionary synthesis of voltage controlled multifunctional logic circuits makes it possible to synthesize more circuits in less time. Prior to the modification, the computations for synthesizing a four-function logic circuit by this method took about 10 hours. Using the method as modified, it is possible to synthesize a six function circuit in less than half an hour.

Posted in: Briefs, TSP, Semiconductors & ICs, Integrated circuits, Integrated circuits

N-Type d Doping of High-Purity Silicon Imaging Arrays

A process for n-type (electron-donor) delta (d) doping has shown promise as a means of modifying back-illuminated image detectors made from n-doped high-purity silicon to enable them to detect high-energy photons (ultraviolet and x-rays) and low-energy charged particles (electrons and ions). This process is applicable to imaging detectors of several types, including charge-coupled devices, hybrid devices, and complementary metal oxide/semiconductor detector arrays.

Posted in: Briefs, TSP, Semiconductors & ICs, Charge coupled devices, Imaging, Imaging and visualization, Semiconductor devices, Sensors and actuators, Charge coupled devices, Imaging, Imaging and visualization, Semiconductor devices, Sensors and actuators, Silicon alloys

Making AlNx Tunnel Barriers Using a Low-Energy Nitrogen-Ion Beam

A technique based on accelerating positive nitrogen ions onto an aluminum layer has been demonstrated to be effective in forming thin (<2 nm thick) layers of aluminum nitride (AlNx) for use as tunnel barriers in Nb/Al-AlNx/Nb superconductor/ insulator/ superconductor (SIS) Josephson junctions. AlNx is the present material of choice for tunnel barriers because, to a degree greater than that of any other suitable material, it offers the required combination of low leakage current at high current density and greater thermal stability.

Posted in: Briefs, Semiconductors & ICs, Aluminum alloys, Materials properties, Nanotechnology, Semiconductors

Making Wide-IF SIS Mixers With Suspended Metal-Beam Leads

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide intermediate frequency band (wide-IF) superconductor/ insulator/ superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25-µm-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections:

Posted in: Briefs, TSP, Semiconductors & ICs, Fabrication, Forming, Semiconductors

Mathematical Modeling of a Copper-Deposition System for Integrated Circuits

Advanced packaging techniques are the key to utilizing state-of-the-art microelectronic devices. The flip-chip method has become a cost-effective means of erasing many packaging and thermal issues that could spell disaster for high-density, high-power integrated circuits (ICs). Making flip-chip receptacles presents significant engineering challenges. To overcome those challenges, Replisaurus developed a unique process that required mathematical modeling to better understand and optimize the patented process.

Posted in: Briefs, Semiconductors & ICs, Mathematical models, Integrated circuits, Integrated circuits, Packaging, Copper

Stripline/Microstrip Transition in Multilayer Circuit Board

A stripline to microstrip transition has been incorporated into a multilayer circuit board that supports a distributed solid-state microwave power amplifier, for the purpose of coupling the microwave signal from a buried-layer stripline to a top-layer microstrip. The design of the transition could be adapted to multilayer circuit boards in such products as cellular telephones (for connecting between circuit-board signal lines and antennas), transmitters for Earth/satellite communication systems, and computer mother boards (if processor speeds increase into the range of tens of gigahertz).

Posted in: Briefs, TSP, Semiconductors & ICs, Amplifiers, Architecture, Integrated circuits, Amplifiers, Architecture, Integrated circuits, Semiconductors

Multifunctional Logic Gate Controlled by Supply Voltage

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that functions as a NAND gate at a power-supply potential (Vdd) of 3.3 V and as NOR gate for Vdd = 1.8 V. In the intermediate Vdd range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics — a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of Vdd.

Posted in: Briefs, TSP, Semiconductors & ICs, Adaptive control, Integrated circuits, Switches, Adaptive control, Integrated circuits, Switches, Semiconductors

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