VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

Rapid processing is made possible by a massively parallel neural-computing architecture.

A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression- assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

Commonly, the design of such an instrument provides for a sample and a reference channel, so that it can be used to perform a dual-label assay for identifying differentially expressed genes. A dual-label assay also reduces spurious variability attributable to aspects of spots in the microarray that affect both the sample and the reference specimen similarly. The logarithm of the relative intensities of the two fluorescent-dye-labeled specimens at each spot is calculated and used in analyzing the fluorescence image of the assay. Heretofore, analysis of the fluorescence image has typically involved sequential, pixel-by-pixel processing in a digital computer. Such processing does not enable real-time recognition of genetic patterns of interest — a significant drawback where, for example, it may be desirable or necessary to recognize dangerous microbes in the field. In contrast, a system like the one now being developed enables robust, real-time recognition.

The system (see figure) includes a chip, denoted a biochip, that contains VLSI circuitry for collecting the fluorescence inputs and generates analog signals proportional to the logarithms of the fluorescence-intensity ratios for the spots in the microarray. The outputs of the biochip are fed as inputs to another chip that contains a VLSI artificial neural network (ANN), which performs the processing for recognition of bioinformatic patterns of interest. The ANN design provides for a combination of massively parallel neural-computing interconnections and mixed-signal (a combination of analog and digital) circuitry characterized by feature sizes in the deep-submicron range, making it possible to implement the ANN as a single VLSI chip. One notable aspect of the design is the use of a parallel row/column data-flow architecture to connect all on-chip subsystems and eliminate data-flow bottlenecks of the type caused by bandwidth limitations in conventional data buses.

The ANN includes input neurons, programmable-weight synapses, summing and inner product cells, output neurons, and an output multi-winner-take-all encoder. The programmable synapse matrix is composed of M×N cells for N×M-dimensional code vectors. There are N output summing neurons that execute a sigmoid-logarithmic (in contradistinction to a conventional sigmoid) transfer function. The synaptic weights are generated by an error-back- propagation supervised-learning algorithm executed by an off-chip host controlling processor. The outputs of the output summing neurons are fed to a multi-winner-take-all block that consists of N competitive circuit cells and uses binary codes to encode N classes.

This work was done by Wai-Chi Fang of Caltech and Jaw-Chyng Lue of University of Southen California for NASA’s Jet Propulsion Laboratory.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:

Innovative Technology Assets Management
JPL
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
(818) 354-2240
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Refer to NPO-44155, volume and number of this NASA Tech Briefs issue, and the page number.