Replication of Space-Shuttle Computers in FPGAs and ASICs
- Created on Monday, 01 December 2008
A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL).
The HDL is synthesized to form a “core” processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.
This work was done by Roscoe C. Ferguson
of United Space Alliance for Johnson Space
This Brief includes a Technical Support Package (TSP).
Replication of Space-Shuttle Computers in FPGAs and ASICs (reference MSC-24141-1) is currently available for download from the TSP library.
Please Login at the top of the page to download.