Commonly, field-programmable gate arrays (FPGAs) being developed in cPCI embedded systems include the bus interface in the FPGA. This complicates the development because the interface is complicated and requires a lot of development time and FPGA resources. In addition, flight qualification requires a substantial amount of time be devoted to just this interface.

The cPCI Interface is a common interface between the cPCI bus and the backend FPGA. It is implemented as a separate interface device on the cPCI bus.
Another complication of putting the cPCI interface into the FPGA being developed is that configuration information loaded into the device by the cPCI microprocessor is lost when a new bit file is loaded, requiring cumbersome operations to return the system to an operational state.

Finally, SRAM-based FPGAs are typically programmed via specialized cables and software, with programming files being loaded either directly into the FPGA, or into PROM devices. This can be cumbersome when doing FPGA development in an embedded environment, and does not have an easy path to flight. Currently, FPGAs used in space applications are usually programmed via multiple space-qualified PROM devices that are physically large and require extra circuitry (typically including a separate one-time programmable FPGA) to enable them to be used for this application.

This technology adds a cPCI interface device with a simple, flexible, high-performance backend interface supporting multiple backend FPGAs. It includes a mechanism for programming the FPGAs directly via the microprocessor in the embedded system, eliminating specialized hardware, software, and PROM devices and their associated circuitry. It has a direct path to flight, and no extra hardware and minimal software are required to support reprogramming in flight. The device added is currently a small FPGA, but an advantage of this technology is that the design of the device does not change, regardless of the application in which it is being used. This means that it needs to be qualified for flight only once, and is suitable for one-time programmable devices or an application specific integrated circuit (ASIC). An application programming interface (API) further reduces the development time needed to use the interface device in a system.

This work was done by Duane I. Clark and Chester N. Lim of Caltech for NASA’s Jet Propulsion Laboratory.

The software used in this innovation is available for commercial licensing. Please contact Daniel Broderick of the California Institute of Technology at This email address is being protected from spambots. You need JavaScript enabled to view it.. NPO-48424

Topics:
Architecture Buses Cables Computer software and hardware Electronic equipment Electronics & Computers Integrated circuits Parts Vehicles
This Brief includes a Technical Support Package (TSP).
Document cover
Flexible Architecture for FPGAs in Embedded Systems

(reference NPO-48424) is currently available for download from the TSP library.

Don't have an account?

Magazine cover
NASA Tech Briefs Magazine

This article first appeared in the September, 2012 issue of NASA Tech Briefs Magazine (Vol. 36 No. 9).

Read more articles from this issue here.

Read more articles from the archives here.

Overview

The document titled "Flexible Architecture for FPGAs in Embedded Systems" describes an innovative interface developed for PCI boards that incorporate Field Programmable Gate Arrays (FPGAs). This interface was initially designed for the proposed Surface Water and Ocean Topography (SWOT) mission but is intended to serve as a universal solution for connecting the PCI bus to various Backend FPGAs, regardless of the specific application.

The interface device operates as a separate entity on the PCI bus, effectively abstracting the complexities associated with PCI bus communication. It supports multiple backend FPGAs and implements three primary data interfaces: a Register Interface, Direct Memory Access (DMA), and Bitfile Loading. These interfaces share a 32-bit data bus and are synchronized with a common clock derived from the PCI clock.

  1. Register Interface: This interface provides a straightforward read/write mechanism, allowing for 32-bit wide transactions. Each register read and write is handled as a separate transaction, with the backend FPGAs signaling valid data during reads.

  2. DMA Interface: The DMA interface supports multiple independent channels for high-speed data transfers. It utilizes First In First Out (FIFO) buffers for each channel, facilitating efficient data handling. The interface employs flags to manage data flow, enabling burst transfers and individual transactions based on the status of these flags.

  3. Bitfile Loading Interface: Specifically for Xilinx FPGAs, this interface allows for the loading of configuration bitfiles via the PCI bus, utilizing the Xilinx SelectMap interface.

Additionally, the document highlights the implementation of serial JTAG control through the PCI bus, which is crucial for boundary scanning and verifying the integrity of the configuration memory against Single Event Upsets (SEUs). The interface is currently implemented in a Xilinx Spartan FPGA, with plans for porting to one-time programmable Actel devices for future flight missions. Its consistent design across applications makes it a strong candidate for ASIC implementation.

The document also notes that Application Programming Interface (API) software has been developed for controlling the interface under the Linux operating system, further enhancing its usability in embedded systems.

Overall, this flexible architecture aims to streamline the integration of FPGAs in embedded systems, providing a robust and adaptable solution for aerospace and other technological applications.