Breadboard Signal Processor for Arraying DSN Antennas

The processors can be used to combine signals in interferometry and telecommunications.

A recently developed breadboard version of an advanced signal processor for arraying many antennas in NASA’s Deep Space Network (DSN) can accept inputs in a 500-MHz-wide frequency band from six antennas. The next breadboard version is expected to accept inputs from 16 antennas, and a following developed version is expected to be designed according to an architecture that will be scalable to accept inputs from as many as 400 antennas. These and similar signal processors could also be used for combining multiple wide-band signals in non-DSN applications, including very-long-baseline interferometry and telecommunications.

This signal processor performs functions of a wide-band FX correlator and a beam-forming signal combiner. [The term “FX” signifies that the digital samples of two given signals are fast Fourier transformed (F), then the fast Fourier transforms of the two signals are multiplied (X) prior to accumulation.] In this processor, the signals from the various antennas are broken up into channels in the frequency domain (see figure). In each frequency channel, the data from each antenna are correlated against the data from each other antenna; this is done for all antenna baselines (that is, for all antenna pairs). The results of the correlations are used to obtain calibration data to align the antenna signals in both phase and delay. Data from the various antenna frequency channels are also combined and calibration corrections are applied. The frequency- domain data thus combined are then synthesized back to the time domain for passing on to a telemetry receiver.

The inputs from the antennas are preprocessed signals in an intermediate- frequency (IF) band from 700 to 1,200 MHz. High-speed commercial offthe- shelf analog-to-digital-converter (ADC) integrated circuits sample the inputs to 8 bits at a rate of 1,280 MHz. The sample data are transmitted via fiber-optic links to signal-processing boards in a commercial high-performance, modular, digital chassis that conforms to an industry standard known as the Advanced Telecommunications Architecture (ATCA). The physical and electrical characteristics of an ATCA chassis are governed by a specification known as PICMG 3.0 (wherein “PICMG” signifies the PCI Industrial Computer Manufacturers Group and “PCI” signifies peripheral component interface).

Mounted on each signal-processing board are four field-programmable gate array (FPGA) integrated-circuit chips that are interconnected both on the board and through the ATCA back plane by serial links capable of operating at speeds up to 2.5 Gb/s. Each FPGA chip can be programmed, independently of the other FPGA chips, to perform such specific functions as implementing filter banks to convert time-domain data to frequencydomain data in frequency channels, wideand narrow-band cross-correlation, combining of the individual frequency channels, and implementing synthesizing filter banks for converting frequencydomain data back to the time domain.

This work was done by Andre Jongeling, Elliott Sigman, Kumar Chandra, Joseph Trinh, Melissa Soriano, Robert Navarro, Stephen Rogstad, Charles Goodhart, Robert Proctor, Michael Jourdan, and Benno Rayhrer of Caltech for NASA’s Jet Propulsion Laboratory.

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