Firmware for implementing a digital phasemeter within a field-programmable gate array (FPGA) has been devised. In the original application of this firmware, the phase that one seeks to measure is the difference between the phases of two nominally-equal-frequency heterodyne signals generated by two interferometers. In that application, zero-crossing detectors convert the heterodyne signals to trains of rectangular pulses (see figure), the two pulse trains are fed to a fringe counter (the major part of the phasemeter) controlled by a clock signal having a frequency greater than the heterodyne frequency, and the fringe counter computes a time-averaged estimate of the difference between the phases of the two pulse trains.
The firmware also does the following:
- Causes the FPGA to compute the frequencies of the input signals;
- Causes the FPGA to implement an Ethernet (or equivalent) transmitter for readout of phase and frequency values; and
- Provides data for use in diagnosis of communication failures.
The readout rate can be set, by programming, to a value between 250 Hz and 1 kHz. Network addresses can be programmed by the user.
This program was written by Shanti R. Rao of Caltech for NASA's Jet Propulsion Laboratory.
The software used in this innovation is available for commercial licensing. Please contact Karina Edmonds of the California Institute of Technology at (626) 395-2322. Refer to NPO-45575.
This Brief includes a Technical Support Package (TSP).
Implementing a Digital Phasemeter in an FPGA
(reference NPO-45575) is currently available for download from the TSP library.
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Overview
The document is a Technical Support Package from NASA, specifically NPO-45575, detailing the implementation of a digital phasemeter in an FPGA (Field-Programmable Gate Array). It outlines the technological advancements and features of the phasemeter, which is designed for precision measurement in various applications, particularly in aerospace and metrology.
Key features of the phasemeter include a 100 kHz heterodyne operation with a 200 MHz clock, achieving a precision of 0.5 x 10^-4 cycles. The device is capable of measuring delays with a jitter of 0.47 ns over 16 seconds, demonstrating its reliability in high-accuracy environments. The document includes a histogram of measured delays, indicating the performance consistency of the phasemeter.
The phasemeter is designed with several selling points: it integrates six phasemeters on a single chip, allowing for scalability in power, cabling, and costs as system size increases. The modular design simplifies the setup, requiring only two wires each for Ethernet, high-quality clock, power, and two fibers for laser light. This design approach emphasizes low weight, low power consumption, low complexity, and low cost, making it suitable for various applications.
The document also highlights ongoing work, including tests with laser metrology systems, power consumption measurements, and the development of higher density FPGA layouts. This indicates a commitment to continuous improvement and adaptation of the technology for broader use.
Additionally, the document serves as a resource for those interested in aerospace-related developments with potential commercial applications. It provides contact information for further inquiries, emphasizing NASA's role in fostering innovative partnerships and technology transfer.
Overall, the Technical Support Package presents a comprehensive overview of the digital phasemeter's capabilities, design objectives, and potential applications, showcasing NASA's efforts to advance technology in precision measurement and its implications for various fields.
