Oxide embedding structures and nanoscale multiplication regions would afford improvements in performance.
Nano- multiplication- region avalanche photodiodes (NAPDs), and imaging arrays of NAPDs integrated with complementary metal oxide/semiconductor (CMOS) active-pixel-sensor integrated circuitry, are being developed for applications in which there are requirements for high-sensitivity (including photoncounting) detection and imaging at wavelengths from about 250 to 950 nm. With respect to sensitivity and to such other characteristics as speed, geometric array format, radiation hardness, power demand of associated circuitry, size, weight, and robustness, NAPDs and arrays thereof are expected to be superior to prior photodetectors and arrays including CMOS active-pixel sensors (APSs), charge-coupled devices (CCDs), traditional APDs, and microchannelplate/ CCD combinations.
Figure 1 depicts a conceptual NAPD array, integrated with APS circuitry, fabricated on a thick silicon-on-insulator wafer (SOI). Figure 2 presents selected aspects of the structure of a typical single pixel, which would include a metal oxide/semiconductor field-effect transistor (MOSFET) integrated with the NAPD. The NAPDs would reside in silicon islands formed on the buried oxide (BOX) layer of the SOI wafer. The silicon islands would be surrounded by oxide-filled insulation trenches, which, together with the BOX layer, would constitute an oxide embedding structure. There would be two kinds of silicon islands: NAPD islands for the NAPDs and MOSFET islands for in-pixel and global CMOS circuits. Typically, the silicon islands would be made between 5 and 10 μm thick, but, if necessary, the thickness could be chosen outside this range. The side walls of the silicon islands would be heavily doped with electron-acceptor impurities (p+- doped) to form anodes for the photodiodes and guard layers for the MOSFETs.
A nanoscale reach-through structure at the front (top in the figures) central position of each NAPD island would contain the APD multiplication region. Typically, the reach-through structure would be about 0.1 μm in diameter and between 0.3 and 0.4 nm high. The top layer in the reach-through structure would be heavily doped with electrondonor impurities (n+-doped) to make it act as a cathode. A layer beneath the cathode, between 0.1 and 0.2 nm thick, would be p-doped to a concentration ≈1017 cm–3. A thin n+-doped polysilicon pad would be formed on the top of the cathode to protect the cathode against erosion during a metal-silicon alloying step that would be part of the process of fabricating the array. This NAPD structure would be amenable to either front or back illumination. To enable back illumination, it would be necessary to etch away, from underneath the NAPD silicon islands, the corresponding portions of a handle wafer supporting the SOI substrate.
The advantages of the NAPD concept over prior photodetector and array concepts are attributable to the oxide embedding SOI structure and the nanoscale multiplication region. The electrically insulating property of the oxide embedding structure would prevent cross-talk among pixels. The nanoscale design of the multiplication region could be tailored to obtain unique avalanche properties. In contrast, (1) the pixels of a traditional APD array are all built on one common substrate, leading to severe cross-talk and (2) a traditional APD contains a relatively large multiplication region, within which electron avalanches are localized to a few small volumes. Efforts have been made to obtain uniformity in the multiplication regions of traditional APDs, but inasmuch as electron avalanches are very sensitive to the local electric-field fluctuations, it is difficult to obtain uniformity in large arrays of conventional APDs.
This work was done by Xinyu Zheng, Bedabrata Pain, and Thomas Cunningham of Caltech for NASA’s Jet Propulsion Laboratory.
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