The Multithreaded Microbenchmarks for Processor-InMemory (PIM) Compilers, Simulators, and Hardware are computer programs arranged in a series for use in testing the performances of PIM computing systems, including compilers, simulators, and hardware. The programs at the beginning of the series test basic functionality; the programs at subsequent positions in the series test increasingly complex functionality. The programs are intended to be used while designing a PIM system, and can be used to verify that compilers, simulators, and hardware work correctly. The programs can also be used to enable designers of these system components to examine tradeoffs in implementation. Finally, these programs can be run on non-PIM hardware (either singlethreaded or multithreaded) using the POSIX pthreads standard to verify that the benchmarks themselves operate correctly. (POSIX -Portable Operating System Interface for UNIX- is a set of standards that define how programs and operating systems interact with each other. pthreads is a library of pre-emptive thread routines that comply with one of the POSIX standards).
These programs were written by Daniel S. Katz of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Semiconductors & ICs category.
This software is available for commercial licensing. Please contact Karina Edmonds of the California Institute of Technology at (818) 393-2827. Refer to NPO-41206.
This Brief includes a Technical Support Package (TSP).
Programs for Testing Processor-in-Memory Computing Systems
(reference NPO-41206) is currently available for download from the TSP library.
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Overview
The document is a Software Reporting Form from the California Institute of Technology's Jet Propulsion Laboratory (JPL), dated December 27, 2005. It outlines the procedures and requirements for disseminating software developed at JPL, specifically focusing on a new software application related to multithreaded microbenchmarks for Processor-In-Memory (PIM) compilers, simulators, and hardware.
The software aims to test various features and performance aspects of the system, allowing for a comprehensive evaluation of its capabilities. The form indicates that the software was developed without relying on previously existing code or software, and it has not been disclosed or distributed externally prior to this report. The document emphasizes the need for permission from non-JPL developers if any contributions were made by external parties, highlighting the importance of intellectual property considerations in software dissemination.
The form also addresses the necessity of obtaining approval for software export, particularly if the software is classified for export. It mentions that the Open Channel process is required for software release, and details about the fields of use for the software must be provided. Additionally, the form inquires about existing websites or publications related to the software, indicating a structured approach to documenting and sharing information about the software's development and applications.
The document includes sections on funding disclosure, where it notes that the software is part of a project funded by DARPA, with estimated development costs and anticipated additional funding. It also outlines the contributors to the software, emphasizing the need to recognize those who made significant contributions to its conception and implementation.
Overall, the Software Reporting Form serves as a comprehensive guide for JPL personnel to navigate the complexities of software dissemination, ensuring compliance with legal and institutional requirements while promoting the sharing of innovative technologies developed at JPL. The document reflects JPL's commitment to transparency and collaboration in advancing aerospace-related technologies, with a focus on the potential commercial applications of their research.
