The IP-EP200 series Industry Pack I/O modules from Acromag (Wixom, MI) interface digital I/O signals to a user-configurable Altera® Cyclone™ II FPGA. With JTAG access to the SignalTap® II embedded logic analyzer, users can monitor internal device operation.
Several models are available to accommodate RS-485 differential, TTL, or LVDS digital I/O signals. All units feature the Cyclone II FPGA device with 20 K logic elements 240 Kb RAM and 26 (18 × 18) embedded multipliers. Three models are available: the first IP-EP200 provides 48 bidirection TTL I/O lines, the second offers 24 differential RS485 I/O lines, and the third has 24 LVDS I/O lines. An additional "combo" model pairs 24 TTL with 12 RS485 I/O lines on a single IP module. The IP-EP200 allows users to develop and store their own instruction set in the FPGA for adaptive computing applications. Memory demands are met via 64 K × 16 local static RAM provided under FPGA control. An LVTTL external clock is connected to the FPGA. The programmable PLL-based clock synthesizer generates frequencies from 250 kHz to 100 MHz. Support for an 8 MHZ and a 32 MHz IP bus is standard.
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