The Mobile Thread Task Manager (MTTM) is being applied to parallelizing existing flight software to understand the benefits and to develop new techniques and architectural concepts for adapting software to multicore architectures. It allocates and load-balances tasks for a group of threads that migrate across processors to improve cache performance.
In order to balance-load across threads, the MTTM augments a basic map-reduce strategy to draw jobs from a global queue. In a multicore processor, memory may be “homed” to the cache of a specific processor and must be accessed from that processor. The MTTB architecture wraps access to data with thread management to move threads to the home processor for that data so that the computation follows the data in an attempt to avoid L2 cache misses. Cache homing is also handled by a memory manager that translates identifiers to processor IDs where the data will be homed (according to rules defined by the user). The user can also specify the number of threads and processors separately, which is important for tuning performance for different patterns of computation and memory access.
MTTM efficiently processes tasks in parallel on a multiprocessor computer. It also provides an interface to make it easier to adapt existing software to a multiprocessor environment.
This work was done by Bradley J. Clement, Tara A. Estlin, and Benjamin J. Bornstein of Caltech for NASA’s Jet Propulsion Laboratory.
This software is available for commercial licensing. Please contact Dan Broderick at
This Brief includes a Technical Support Package (TSP).
Mobile Thread Task Manager
(reference NPO-48425) is currently available for download from the TSP library.
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Overview
The document outlines advancements in rover science operations at NASA's Jet Propulsion Laboratory (JPL), focusing on the integration of multi-core computing to enhance rover autonomy technologies for future missions. The primary objective of the work was to adapt three key technologies to a multi-core processor, specifically the Tilera Tile64, to improve onboard data analysis and decision-making capabilities.
The first technology adapted was the MER AEGIS image analysis system, which is used for rock-finding in images. The second was an image analysis approach for terrain texture classification, enabling the identification of various rock types and terrain features. The third technology was the CASPER (Continuous Activity Scheduling, Planning, and Re-planning) system, which automates the generation and modification of spacecraft command sequences based on real-time rover states and constraints.
The document details a comprehensive performance evaluation of these technologies on the multi-core system, assessing metrics such as runtime performance, memory/cache profiling, and load balancing. The results indicated significant performance gains, demonstrating how multi-core computing can enhance rover autonomy and enable high-rate data collection and analysis onboard, reducing reliance on ground communications.
Additionally, the document discusses the significance of these advancements for future missions, particularly the Mars Sample Return (MSR) mission and other exploratory missions to small bodies like asteroids and comets. The ability to perform rapid onboard data analysis and re-planning is crucial for identifying and sampling high-priority science targets within limited mission timelines.
The work also emphasizes the importance of fault tolerance in multi-core systems, detailing the development of a fault model for the Tile64 processor and adaptive fault tolerance methods to ensure reliability during rover operations. This research supports a new class of onboard computing that can significantly enhance the capabilities of future space missions.
In summary, the document highlights the strategic focus on fault-tolerant scalable flight computing and the potential of multi-core processing to revolutionize rover science operations, paving the way for more autonomous and efficient exploration of planetary bodies. The findings contribute to JPL's goals of integrating advanced computing technologies into future autonomous flight missions.
