Analog-to-digital converters (ADCs) are used in scientific and communications instruments on all spacecraft. As data rates get higher, and as the transition is made from parallel ADC designs to high-speed, serial, low-voltage differential signaling (LVDS) designs, the need will arise to interface these in field-programmable gate arrays (FPGAs). As Xilinx has released the radiation-hardened version of the Virtex-5, this will likely be used in future missions.
High-speed serial ADCs send data at very high rates. A de-serializer instantiated in the fabric of the FPGA could not keep up with these high data rates. The Virtex-5 contains primitives designed specifically for high-speed, source-synchronous de-serialization, but as supported by Xilinx, can only support bit-widths of 10. Supporting bit-widths of 12 or more requires the use of the primitives in an undocumented configuration, a non-trivial task.
De-serializing the bits from high-speed ADCs running at speeds of 50 Msps or more becomes a non-trivial problem in the Xilinx Virtex-5. The bit clock speeds are very high (300 MHz or more), and the ADC sample width can be wider than what the built-in Virtex-5 ISERDES_NODELAY primitives officially support (12 bits or more). The Virtex-5 User Guide does not specify how to configure the ISERDES_NODELAY primitives for such higher bit-widths.
A new SystemVerilog design was written that is simpler and uses fewer hardware resources than the reference design described in Xilinx Application Note XAPP866. It has been shown to work in a Xilinx XC5VSX24OT connected to a MAXIM MAX1438 12-bit ADC using a 50-MHz sample clock. The design can be replicated in the FPGA for multiple ADCs (four instantiations were used for a total of 28 channels).
This work was done by Gregory H. Taylor of Caltech for NASA’s Jet Propulsion Laboratory. The software used in this innovation is available for commercial licensing. Please contact Daniel Broderick of the California Institute of Technology at
This Brief includes a Technical Support Package (TSP).
High-Speed, Multi-Channel Serial ADC LVDS Interface for Xilinx Virtex-5 FPGA
(reference NPO-48191) is currently available for download from the TSP library.
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Overview
The document is a Technical Support Package from NASA's Jet Propulsion Laboratory (JPL) detailing the High-Speed, Multi-Channel Serial Analog-to-Digital Converter (ADC) LVDS Interface for the Xilinx Virtex-5 FPGA. It serves as a comprehensive guide for engineers and researchers involved in aerospace technology, particularly in the context of high-speed data acquisition systems.
The document begins with an abstract and an overview of the ADC, emphasizing its significance in high-speed applications. It outlines the timing diagram of the ADC output, which is crucial for understanding the synchronization of data transmission. A key feature discussed is the Virtex-5 support for high-speed source-synchronous deserialization, which allows for efficient data handling and processing.
A block diagram of the design is provided, illustrating the architecture and components involved in the ADC system. The design details section elaborates on critical aspects such as the treatment of the frame clock, which is processed similarly to data signals through the ISERDES_NODELAY primitives. This ensures that the timing of the frame clock aligns with that of the data, maintaining synchronization.
The document also addresses the IODELAY configuration on the bit clock input. It explains how the bit clock, after passing through a BUFIO, can introduce skew that may affect timing requirements. The use of the IODELAY primitive is highlighted as a solution to realign the bit clock as necessary, ensuring that the design meets timing specifications. The calibration of delay taps using the IODELAYCTRL primitive is discussed, along with the results of post-place-and-route (PAR) back-annotated timing simulations that confirmed the correctness of data output.
Additional sections cover design restrictions, simulation methodologies, and a top-level module description, including SystemVerilog module definitions, parameters, and signals. The document concludes with a file list and tools used in the design process, providing a comprehensive resource for those looking to implement or understand the high-speed ADC LVDS interface.
Overall, this Technical Support Package encapsulates the challenges and solutions associated with high-speed data acquisition in aerospace applications, offering valuable insights and practical guidance for engineers and researchers in the field.
