A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven inflight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).
This work was done by Allen Farrington, Andrew Gray, Bryan Bell, Valerie Stanton, Yong Chong, Kenneth Peters, Clement Lee, and Jeffrey Srinivasan of Caltech for NASA’s Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Electronics/ Computers category.
This software is available for commercial licensing. Please contact Karina Edmonds of the California Institute of Technology at (818) 393-2827. Refer to NPO-30357.
This Brief includes a Technical Support Package (TSP).
Software-Reconfigurable Processors for Spacecraft
(reference NPO-30357) is currently available for download from the TSP library.
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Overview
The document is a Technical Support Package from NASA's Jet Propulsion Laboratory, focusing on Software-Reconfigurable Processors for spacecraft, specifically under the NASA Tech Briefs NPO-30357. It outlines the development and potential applications of reconfigurable network processors designed to enhance spacecraft capabilities in communications, navigation, and science data processing.
At the core of the document is the concept of a space-based reconfigurable network processor that serves multiple functions, including acting as a communications infrastructure, a science instrument, and a navigation processor. The architecture is based on the OSI network model, incorporating various layers such as the physical, data link, network, transport, and application layers. This design allows for concurrent mission reconfigurability and rapid prototyping of diverse signal processing functions.
The document emphasizes the importance of reconfigurability, which enables mission planners to modify science processing in response to data acquired during missions. This adaptability is crucial for deep space missions, where communication challenges differ significantly from terrestrial environments. The document discusses the potential for on-orbit reconfiguration of the network processor, allowing for updates and enhancements to processing capabilities even after launch.
Figures included in the document illustrate the architecture and functionality of the reconfigurable processor, showcasing its implementation using a Xilinx field-programmable gate array (FPGA) and a Power PC processor. The integration of hardware and software components is highlighted, demonstrating how the configuration can be controlled through software, thus allowing for flexible and efficient processing.
Additionally, the document addresses the challenges of deep space communications, particularly the need for power-efficient transmission of information over vast distances. It discusses modern error-control coding techniques, such as turbo-codes and low-density parity check codes, which can significantly improve transmission efficiency. However, it also notes the computational complexity of implementing optimal decoders for high data rates, suggesting that future advancements may simplify these implementations.
Overall, the document presents a forward-looking perspective on the use of software-reconfigurable processors in space missions, emphasizing their potential to enhance mission flexibility, efficiency, and scientific output. It serves as a resource for understanding the technological advancements in aerospace applications and the ongoing efforts to improve spacecraft systems.
