A document discusses placing memory modules on the high-speed serial interconnect, which is used by a spacecraft’s computer elements for inter-processor communications, to allow all multiple computer system architectures to access the spacecraft data storage at the same time. Each memory board is identical electrically and receives its bus ID upon connection to the system. The computer elements are configured in a similar fashion. The architecture allows for multiple memory boards to be accessed simultaneously by different computer elements, and results in a scalable, strong, fault-tolerant system. The IEEE-1393 ring bus can be routed so that multiple card failures can occur and the mass memory storage will still function.

This work was done by Brian Cox of Caltech for NASA’s Jet Propulsion Laboratory.

NPO-45204



This Brief includes a Technical Support Package (TSP).
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Network-Attached Solid-State Recorder Architecture

(reference NPO-45204) is currently available for download from the TSP library.

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NASA Tech Briefs Magazine

This article first appeared in the November, 2008 issue of NASA Tech Briefs Magazine (Vol. 32 No. 11).

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Overview

The document is a Technical Support Package from NASA's Jet Propulsion Laboratory (JPL) detailing the Network-Attached Solid-State Recorder (SSR) Architecture, identified as NPO-45204. It addresses the limitations of traditional spacecraft data storage systems, which typically rely on point-to-point communication links between computer elements and SSRs. As spacecraft architectures evolve to incorporate multiple computer systems that require simultaneous access to storage, the existing point-to-point interconnects become inadequate.

To overcome these challenges, the document introduces a new architecture that utilizes a high-speed serial interconnect, specifically the IEEE 1393, designed for inter-processor communications. This innovative approach allows for multiple memory boards to be connected in a ring configuration, enabling simultaneous access by different computer elements without interference. Each memory board is identical and receives a unique bus ID upon connection, contributing to a scalable and robust fault-tolerant system.

The architecture enhances reliability by creating fault containment regions for each memory board, ensuring that the mass memory storage continues to function even if multiple card failures occur. This level of fault tolerance is a significant improvement over traditional SSRs, which do not support such resilience. The new system is designed to be flexible, accommodating various spacecraft architectures currently under investigation.

The document emphasizes the importance of highly reliable mass memory for NASA's spacecraft, noting that this new architecture could improve reliability, increase scalability, and potentially reduce costs compared to existing SSRs. The advancements presented in this Technical Support Package are positioned to have broader technological, scientific, and commercial applications, aligning with NASA's goals in aeronautical and space activities.

For further inquiries or assistance, the document provides contact information for the Innovative Technology Assets Management at JPL, indicating a commitment to collaboration and innovation in aerospace technology. Overall, the Network-Attached Solid-State Recorder Architecture represents a significant step forward in the design and functionality of spacecraft data storage systems, addressing contemporary needs and future challenges in space exploration.