Analysis and Simulation of Low-Light INL in CMOS Image Sensors

With the increase in demand for higher resolution image sensors, pixel pitch has been reduced to fit a larger number of pixels within the same sensor size. In order to read at the same frame rate, multiple rows must be read concurrently. This requires multiple analog to data converters (ADCs) per pixel pitch. ADC pitch has been reduced even further as a result, requiring a tighter layout. The likelihood of parasitic coupling increases, which manifests as electrical crosstalk. In single-slope ADC architecture, ADCs have some shared common nets, including supplies, grounds, biases and ramp. A larger number of ADCs converting at the same time can cause kickback on these shared nets. This can lead to non-idealities, one of which is nonlinearity.

Figure 1. Column-parallel readout architecture. (Image: Forza Silicon)

In addition to traditional sources of nonlinearity, array-level effects become more visible due to the larger and denser array size of the ADCs. These can cause dips in the linearity plot which are tedious to correct and require multiple correction curves. Traditionally, optically black columns are used for row noise correction and offset cancellation. Since they all have similar signal levels, they convert at the same time and introduce a disturbance on shared nets. This can create nonlinearity in the darker regions of an image, which is more apparent to the human eye. In addition, the number of ADC conversions in the dark can change depending on the scene. As a result, the magnitude of the disturbance varies and makes it more difficult to correct. It is therefore better to eliminate the problem at the source.

Single-Slope ADC and Linearity

Figure 2. A typical single-slope ADC. The pixel column bus is read using CDS operation. (Image: Forza Silicon)

Column-parallel ADC architecture and a single-slope ADC schematic are shown in Figure 1 and Figure 2 respectively. The ADCs use correlated double sampling (CDS) to read the pixel voltage. Auto-zeroing (AZ) is completed with respect to the pixel reset level. The ramp is held at a fixed reference level and the pixel TG level is sampled. This level is compared with a ramp signal ranging from high to low in this scenario. At the moment the ramp signal and TG level are the same, a latch pulse is generated.

This pulse is used to latch the counter value, which is the desired digital code corresponding to the pixel signal. In an ADC array, there is one ADC per column bus line. The supplies, grounds, biases and ramp are shared by all the ADCs in the array. As a result, any disturbances on these shared nets —which are caused by kickback as sections of the ADC array convert simultaneously —will be common for all the ADCs when reading a particular row. Traditionally, optically dark columns are added on the side of the active pixel array for correcting any row noise or fixed offsets.

Linearity measures the difference between the measured output and the ideal output. It is quantified in terms of integrated nonlinearity (INL). The typical sources of INL in CMOS image sensors include the pixel output source follower, VLN current source, ramp, the sampling capacitor at the ADC front-end, and the preamplifier. The contribution of the pixel source follower to INL is primarily due to the body effect, which increases the threshold voltage of the device as the source voltage increases. This is known as dark signal (Figure 3). VLN current changes as the drain-source voltage of the VLN device varies (channel length modulation). Variation in the VLN current affects the transconductance (gm) of the output source follower of the pixel, making its gain signal dependent (1) where Rs is output impedance of VLN.

Figure 3. Source follower and the resulting body effect on its output. (Image: Forza Silicon)

Using a cascode VLN current source helps to reduce the effect of channel length modulation. However, this has the side effect of reducing the usable range of the pixel signal as the VLN device can get out of saturation at bright signal levels. Ramp is another major source of INL, particularly at dark signal levels, due to the finite resistance of the current source in the ramp generator. Finally, in the ADC, the primary sources of INL are the sampling circuit and the preamp. Sampling circuit INL occurs because of the signal-dependent resistance of the switch and the signal-dependent capacitance of the sampling cap, which affects the settling error of the pixel reset level and pixel TG level.

Sources of Low-Light INL and Possible Solutions

As described in Section 2, the ADCs all share the supply/ ground, biases and ramp. If a significant number of ADCs convert simultaneously, a kickback will occur on the shared nets. Since CDS is used to cancel random offsets of the pixels and ADCs, conversions for the same signal level occur in close proximity. As a result, if multiple ADCs are converting the same signal level, significant kickback will result in INL. This effect is more prominent in the dark signal region where the temporal noise of the pixel and the ADC dominate photon shot noise. The ADCs converting a brighter signal level have more shot noise and do not convert at the same time, which results in a more distributed kickback. In addition to optically black columns, the number of ADCs converting in the dark signal region can change depending on the scene. The disturbance also has a spatial component, with the ADCs close to the source of the disturbance experiencing larger kickback, resulting in larger INL. As a result, INL will be scene-dependent in both magnitude and spatial distribution, which is very difficult to correct in post-processing. Reducing the INL on the chip is hence desirable.

This formula explains variation in the VLN current affects the transconductance (gm) of the output source follower of the pixel, making its gain signal dependent (1) where Rs is output impedance of VLN. (Image: Forza Silicon)

Ramp is a major source of INL. The ADCs converting the active array will have bumps in their INL plot at low-light levels due to a disturbance in ramp slope. The magnitude of the disturbance will be reduced in ADCs farther from the source, as low pass filters from the RC parasitic on the ramp distribution routing. The disturbance on the ramp is caused by the kickback effect from the preamp output transition, via parasitic capacitance to ramp. Due to small ADC pitch, tighter routing is required, making it more difficult to isolate the ramp.

Figure 4. Miller capacitance in preamp. (Image: Forza Silicon)

If the percentage of aggressors increase, depending on the scene, kickback will increase. Careful consideration should be given to the ramp routing when creating a layout for the ADC column. Another source of parasitic coupling is the CGD of the input MOSFET of the preamp (Figure 4). These devices are designed to have a large W and L to reduce flicker noise, and hence have a larger associated capacitance. Using a cascode configuration on the preamp helps to reduce the Miller effect of the capacitance.

Another source of disturbance is the comparator bias. The disturbance can be on the bias itself, or on the supply/ground to which it is referenced. This is caused by the CGD of the current source (i.e., the same mechanism as preamp). The supply/ground disturbance is caused by sudden IR drop when the comparator output switches. The IR drop level can become large as the current is not negligible, especially when many ADCs convert simultaneously, or when impedance of supply and ground is large, for example, due to the limited number of metal layers.

Figure 5. Variation in ADC conversion due to difference in transition time. (Image: Forza Silicon)

As a result of current trends to move to higher resolution in the same image sensor format and a higher frame rate, ADC pitch has been decreasing to fit more ADCs and achieve the specification. But because the size of the sensor is not also being adjusted, the routing for the supply and ground nets has not improved by the same factor. The IR drop causes a change in the VGS of the comparator bias, which results in a change in current for the victim ADCs comparator. In turn, noise on the bias current alters the transition time of the comparator, which can manifest as nonlinearity (Figure 5).

The nonlinearity becomes more significant for faster ADC count rates, which are used to reduce effective row time to achieve high frame rate. To reduce the disturbance, there are multiple options. First, the drive strength of the bias generator can be increased to decrease the impedance of the bias node, which will help in a faster settling of the disturbance. Second, the number of fast switching gates on the same power domain can be decreased, which aids in the reduction of the IR drop on the supply/ground. This is accomplished by moving these devices to a different power domain. Careful consideration should also be given to minimizing supply/ground routing resistance.

Another approach is to reduce the effect of the glitch on the victim ADCs. This can be achieved by sampling the bias voltage in each ADC separately. As a result, the disturbance will not propagate through the bias net; any disturbance on the supply/ground will be mirrored on the sampled bias voltage, maintaining the same VGS. Proper care should be taken to size the sampling cap so the supply/ground disturbance does not change the VGS. A trade-off of sampling the comparator bias voltage is the introduction of kTC noise. Since the comparator follows the preamplifier in the signal chain, the effect of kTC on the input-referred ADC temporal noise is usually insignificant.

Figure 6. INL Simulation testbench. In this diagram, the ADC array is divided into nine sections. (Image: Forza Silicon)

To investigate this effect, the ADC array is modeled and INL plotted. Routing resistance for all the supplies, grounds, biases and ramp is modeled in the simulation testbench. The references —ramp and biases —are routed horizontally. Supplies and grounds are routed horizontally and vertically. The ADC array is modeled by dividing it into sections and using m-factor. Special care is taken in deciding on the number of sections needed to model the array so that any supply/ground-related variation can be simulated in a reasonable runtime. Dark columns are also included in the testbench. The ADCs are RC extracted so the effect of parasitic capacitance can be seen in the results. Vertical routing for the supplies and ground is carefully modeled to represent actual routing in the sensor. The testbench is set up so that a section of the array is kept at a fixed dark signal level. The input to the remainder of the ADCs in the array is swept to their INL plot. Linearity of each section is compared to determine if there is any spatial pattern. The block diagram of the testbench is shown in Figure 6.

Figure 7. INL plot comparison. (Image: Forza Silicon)

The simulation result before and after modifications is shown in Figure 7. The INL plot is for the first 25 percent of the signal range. The original result displays the INL plot, with no modifications. The next two plots show the INL with the modifications mentioned in the previous section. In one plot the comparator bias is not sampled, while in the other case the comparator bias is sampled. As can be seen, the INL improves significantly when the comparator bias is sampled.

This article has presented an analysis and simulation methodology for predicting the low-light nonlinearity in an ADC array. Conventional sources of INL are well understood, but as pixel array resolution has increased and ADC pitch has consequently been reduced, additional array sources of nonlinearity have become prominent. Multiple possible sources can affect the common nets in an ADC array, most prominently ramp and biases. Methods to reduce this disturbance are presented, which require some careful design choices. A method to identify the sources is also presented, which requires careful modeling of the ADC array. Simulated results reveal a dip in INL at low code levels that improves following modifications.

This article was written by Jatin Hansrani, Senior Analog Design Engineer, Forza Silicon Corporation (Pasadena, CA). For more information visit here .