A short report discusses the technical background of, and the need for, special bus-driver software for part of a test-bed computer system that is to be used in experimentation for development of advanced avionics. The system features a scalable, fault-tolerant, distributed architecture that incorporates a variety of commercial standard bus interfaces. The special bus-driver software is needed to overcome an incompatibility between (1) a Power PC 750 processor made by a first manufacturer and (2) an IEEE 1394 bus-interface circuit board made by a second manufacturer for use in conjunction with a different version of the Power PC 750 made by a third manufacturer. The hardware-related portions of source code of the driver software of the IEEE 1394 board from the second manufacturer was modified and ported to the power PC 750 processor from the first manufacturer. The source code as thus modified has been found to perform successfully and is now in use in the test bed.
This work was done by Minh Lang, Savio Chau, and Tom Huynh of Caltech for NASA’s Jet Propulsion Laboratory. To obtain a copy of the report, “IEEE 1394 bus driver software for the Synergy Power PC 750 processor,” access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp under the Information Sciences category.
This software is available for commercial licensing. Please contact Don Hart of the California Institute of Technology at (818) 393-3425. Refer to NPO-30284.
This Brief includes a Technical Support Package (TSP).
Technical Background of Special Bus-Driver Software
(reference NPO-30284) is currently available for download from the TSP library.
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Overview
The document outlines the development of special bus-driver software for a multi-mission Proof-of-Concept (POC) Testbed facility, created by the Center for Space Integrated Microsystem (CISM) at NASA's Jet Propulsion Laboratory (JPL). This testbed is designed to support advanced avionics technologies and architectures, addressing critical challenges such as power, performance, mass, volume, reliability, and fault tolerance for future missions.
The POC Testbed features a scalable, fault-tolerant, and distributed architecture that incorporates various commercial standard bus interfaces, including IEEE 1394 and I2C buses. The architecture consists of a network of computing nodes connected by redundant bus sets, allowing the system to continue operating even in the event of a node or bus failure. Each computing node is built on a Compact PCI chassis housing two Power PC 750 processors, one serving as the main processor and the other simulating sensors or actuators.
A significant challenge arose due to incompatibility between the IEEE 1394 bus interface board manufactured by Mindready and the Synergy Power PC 750 processor from Synergy Microsystems. The original software driver for the IEEE 1394 board was developed for a different version of the Power PC 750 from Motorola, leading to compatibility issues. To resolve this, the development team acquired the source code for the driver and modified the hardware-related portions to ensure compatibility with the Synergy Power PC 750. This modified driver has been successfully ported and is currently operational within the testbed.
The document emphasizes the importance of flexibility in the testbed's design, allowing it to accommodate various advanced technologies and perform a wide range of architectural experiments. The successful integration of the modified bus-driver software demonstrates the potential for future missions to leverage advanced avionics technologies effectively.
The work was conducted by Minh Lang, Savio Chau, and Tom Huynh, and the software is available for commercial licensing through the California Institute of Technology. The document serves as a technical background report, detailing the motivation, problem, and solution associated with the development of the special bus-driver software, highlighting its significance in advancing avionics experimentation and technology integration for NASA's future missions.
