For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction.
Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (Vth, for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (Vdd) and threshold voltage (Vth) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region.
To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate.
This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.
This work was done by Tuan A. Duong of Caltech for NASA’s Jet Propulsion Laboratory.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:
Innovative Technology Assets Management NPO-47337
JPL
Mail Stop 202-233
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Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI
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Overview
The document outlines research conducted by Tuan A. Duong and his team at NASA's Jet Propulsion Laboratory (JPL) on the "Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption in VLSI Circuits." The primary objective of this research is to explore innovative technology that optimally biases the body of VLSI field-effect transistors (FETs) operating in the weak inversion regime, significantly reducing power consumption without compromising speed.
As VLSI technology advances, particularly with transistor feature sizes shrinking to 50 nm and below, power consumption—both dynamic and leakage—has become a critical constraint. The document emphasizes that while miniaturization allows for more functional components on a chip, it also leads to increased power consumption, particularly due to leakage currents.
The research demonstrates that operating transistors in the sub-threshold region can achieve a two orders of magnitude reduction in power consumption compared to conventional CMOS operations. This is supported by theoretical foundations and simulation results for inverter and SRAM designs. The dynamic threshold approach is highlighted as a powerful technique to minimize power consumption, which is crucial for future cost-effective NASA missions.
Key findings include the ability to reduce dynamic power consumption significantly while also enhancing speed response and reducing leakage power. The document discusses the theoretical basis for these improvements, including the relationship between threshold voltage, body bias, and power consumption. It also introduces the concept of sub-threshold slope as a quality indicator for device performance.
The benefits of this research extend beyond aerospace applications, suggesting that miniaturized systems could enable sophisticated, low-cost missions with compact avionics, thereby impacting system design and operational costs. However, the document also notes challenges, such as increased leakage current and slower response times when operating in the weak inversion region.
In conclusion, the Optimal Dynamic Sub-Threshold Technique represents a promising advancement in VLSI technology, aiming to meet the demands for low power consumption in future system-on-a-chip designs while maintaining high performance. The research is positioned as a significant contribution to the field, with implications for both NASA and broader technological applications.
