A report discusses integrating multiple memory modules on the high-speed serial interconnect (IEEE 1393) that is used by a spacecraft’s inter-module communications in order to ease data congestion and provide for a scalable, strong, flexible system that can meet new system-level mass memory requirements.
Using the JPL 1393 Ring Bus Interconnect to link computer elements, I/O, and memory allows any element to communicate with any other element. Besides providing a consistent approach to exchanging data, it inherently has a layer of abstraction that allows for better system and software design. This new architecture is fault-tolerant and provides a large range of scalability while supporting flexible spacecraft architectures that are currently being investigated.
This work was done by Brian Cox, Jeffrey Mellstrom, and Terry Wysocky of Caltech for NASA’s Jet Propulsion Laboratory.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:
Innovative Technology Assets Management
JPL
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
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Refer to NPO-45205, volume and number of this NASA Tech Briefs issue, and the page number.
This Brief includes a Technical Support Package (TSP).
System-Level Integration of Mass Memory
(reference NPO-45205) is currently available for download from the TSP library.
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Overview
The document titled "System-Level Integration of Mass Memory" from NASA's Jet Propulsion Laboratory (JPL) discusses advancements in spacecraft data storage architecture, specifically focusing on the integration of mass memory using the JPL 1393 Ring Bus interconnect. Traditional spacecraft architectures have relied heavily on Solid State Recorders (SSR) for data storage, which typically utilize point-to-point communication links. This approach has led to challenges in managing a large number of interconnects, particularly for high-rate data-intensive spacecraft.
The motivation behind this new architecture stems from the limitations of traditional SSRs, which do not scale well with increasing interconnects required for future missions. The proposed solution integrates multiple memory modules onto a high-speed serial interconnect, specifically the IEEE 1393 Ring Bus, which has been designed by JPL. This integration allows for a more efficient data management system, reducing congestion and enhancing scalability.
The document outlines several key advantages of the new memory architecture. Firstly, it provides a high level of inherent reliability, as each memory board acts as a fault containment region. This design supports fault tolerance, allowing the system to continue functioning even in the event of multiple card failures. Additionally, the architecture supports simultaneous access to multiple memory boards by different system elements, including computers and I/O devices, which is not feasible with traditional SSRs.
The architecture is also noted for its flexibility, accommodating various spacecraft designs currently under investigation. By allowing memory modules to be placed anywhere on the Ring Bus, the system can be optimized for minimal data latency and congestion. This innovative approach not only improves reliability and scalability but may also reduce costs compared to existing SSR solutions.
The document emphasizes the critical importance of highly reliable mass memory for NASA's spacecraft, as it is essential for the success of numerous missions. The integration of the JPL 1393 Ring Bus into mass memory systems represents a significant advancement in aerospace technology, promising to enhance the performance and efficiency of future space missions.
In summary, the document presents a comprehensive overview of a novel mass memory architecture that addresses the limitations of traditional SSRs, offering a scalable, reliable, and cost-effective solution for NASA's evolving data storage needs in space exploration.
