High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including “Context Modeler for Wavelet Compression of Hyperspectral Images” (NPO-43239) and “ICER-3D Hyperspectral Image Compression Software” (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs).
The design takes advantage of industry-standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes.
The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W.
The reconfigurability (by means of reprogramming) of the FPGAs makes it possible to effectively alter the design to some extent to satisfy different requirements without adding hardware. The implementation could be easily propagated to future FPGA generations and/or to custom application-specific integrated circuits.
This work was done by Nazeeh Aranki, Jeffrey Namkung, Carlos Villalpando, Aaron Kiely, Matthew Klimesh, and Hua Xie of Caltech for NASA’s Jet Propulsion Laboratory. For more information, download the Technical Support Package (free white paper) at www.techbriefs.com/tsp under the Electronics/Computers category. NPO-42834
This Brief includes a Technical Support Package (TSP).
Reconfigurable Hardware for Compressing Hyperspectral Image Data
(reference NPO-42834) is currently available for download from the TSP library.
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Overview
The document discusses a technical support package from NASA's Jet Propulsion Laboratory (JPL) focused on the challenges and solutions related to hyperspectral data compression. Hyperspectral imaging instruments generate vast amounts of data, which can overwhelm storage capabilities and complicate real-time processing during space missions. To address these issues, the document presents an efficient hardware solution utilizing Field Programmable Gate Arrays (FPGAs).
The proposed solution is a scalable FPGA implementation of a progressive 3D reversible wavelet-based algorithm that offers both lossless and lossy compression. This dual capability is crucial for meeting the diverse needs of various missions. The implementation enhances compression effectiveness by exploiting the correlation between spectral bands through a spectral context modeler, ensuring high throughput while maintaining low power consumption.
Key features of the FPGA implementation include:
- Scalability: The design allows for the combination of multiple hardware cores in parallel, which increases throughput to meet demanding mission requirements.
- Efficient Module Design: It includes optimized implementations of essential components of the compression algorithm, such as the 3D wavelet transform, context modeler, and entropy coder.
- On-chip Processing: The embedded PowerPC Reduced Instruction Set Computer (RISC) core manages the overall operation, including scheduling and monitoring processing activities.
- Memory Utilization: The design efficiently utilizes off-chip memory through internal buffering, minimizing intensive input/output operations.
- Reconfigurability: The FPGA's reconfigurable nature allows for in situ reprogramming to adapt to different mission needs without requiring additional hardware. This flexibility also facilitates migration to future FPGA generations or custom ASICs if necessary.
The document emphasizes the novelty of this high-speed, low-power hardware implementation, which is specifically designed for on-board compression of hyperspectral data. It targets the Xilinx Virtex II Pro FPGA family, showcasing its potential for significant advancements in data management for space missions.
For further inquiries or detailed information, the document provides contact details for the Innovative Technology Assets Management at JPL. Overall, this technical support package highlights a significant advancement in the field of aerospace technology, aiming to enhance the efficiency of data handling in hyperspectral imaging applications.
