The design of a highly reliable controller for a digital data bus incorporates improvements, in both hardware and software, over the basic design of a low-speed, low-power, serial bus known in the industry as "I2C." ("I2C" signifies "inter integrated circuit bus" — a bus developed by Philips Semiconductors in the early 1980s.) The original design of the I2C bus lacks fault-tolerant features that could protect against bit errors, shorting of output drives, or babbling nodes (nodes that misbehave or disrupt normal communication). The present design adds such features: It augments the standard I2C bus protocol with low-overhead error-detection features and a fail-silent messaging system, and it adds hardware features that automatically isolate babbling nodes. These fault-tolerant features can be disabled through software (for example, to aid testing), but the design makes it difficult to do this accidentally.

  • The principal advantages of the present design over prior I2C-bus designs are the following:
  • Cyclic redundancy checking (CRC) is used to obtain partial immunity to errors in messages on the bus.
  • Devices on the bus are inhibited from monopolizing the bus, even when hardware or software faults occur.
  • Special commands have been added to enable direct control of one node by another
  • Asynchronous logic in the basic design has been replaced with synchronous logic.

In addition, the bus is compatible with devices that have been designed to function on previously designed, standard versions of the I2C bus.

The overall function of a controller according to the present design is that of an interface between a peripheral component interface (PCI) bus and an I2C bus. The design calls for some basic I2C bus-controller components and associated logic circuitry for a (PCI) port, plus application-specific integrated circuits (ASICs) that implement logic functions to manage the flow of messages and to exert digital input/output (DIO) control. Additional logic circuits are used as watchdog timers and to effect CRC. On each DIO ASIC, there are two I2C bus controllers that drive separate system and subsystem busses. Within each I2C bus controller, there are two I2C commercial-off-the-shelf I2C cores. A transmitting line and a clock line between the cores are ANDed together to make them share a common clock and a data-transmission driver with a separate mixed-signal ASIC.

This work was done by Ryan Fukuhara, Huy Luong, Robert Rasmussen, Savio Chau, and Leonard Day of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp  under the Electronic Components and Systems category.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to

Intellectual Property group
JPL
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109
(818) 354-2240

Refer to NPO-20876, volume and number of this NASA Tech Briefs issue, and the page number.

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This Brief includes a Technical Support Package (TSP).
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Design of a highly reliable controller for an I2C bus

(reference NPO-20876) is currently available for download from the TSP library.

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Overview

The document presents a technical disclosure from NASA regarding the design of a highly reliable controller for the I2C (Inter-Integrated Circuit) bus protocol. The I2C bus is widely used for communication between microcontrollers and various peripherals in embedded systems. However, traditional implementations can be susceptible to faults and communication errors, which can compromise system reliability.

To address these issues, the document outlines significant enhancements made to the original I2C protocol, focusing on fault tolerance and improved data integrity. Key features of the new design include the implementation of cyclic redundancy checking (CRC), which allows for error detection in transmitted data. This mechanism ensures that any corruption during data transfer can be identified and addressed, thereby enhancing the reliability of communication.

Additionally, the document discusses mechanisms to prevent bus monopolization, a situation where a single device could dominate the bus and hinder communication with other devices. By introducing protocols that allow for fair access to the bus, the design promotes a more balanced and efficient communication environment among multiple devices.

The document also emphasizes the importance of hardware and software improvements that contribute to the overall robustness of the I2C controller. These enhancements are aimed at ensuring that the controller can operate effectively in various conditions, including those that may be encountered in space missions or other critical applications.

Furthermore, the technical disclosure includes specific requirements for the I2C controller, detailing the necessary specifications and performance metrics that must be met to achieve the desired level of reliability. This includes considerations for power consumption, response time, and compatibility with existing I2C devices.

In summary, the document serves as a comprehensive overview of NASA's innovative approach to enhancing the I2C bus protocol through a reliable controller design. By focusing on fault tolerance, data integrity, and equitable access to the communication bus, the proposed improvements aim to significantly enhance the performance and reliability of I2C-based systems, making them more suitable for demanding applications in aerospace and other fields.