Objects in our daily lives, such as speakers, refrigerators, and even cars, are becoming “smarter” day by day as they connect to the Internet and exchange data, creating the Internet of Things (IoT). Toward an IoT-based society, a miniaturized thermoelectric generator is anticipated to charge these objects, especially for those that are portable and wearable.

Due to advantages such as its relatively low thermal conductance but high electric conductance, silicon nanowires have emerged as a promising thermoelectric material. Silicon-based thermoelectric generators conventionally employed long, silicon nanowires of about 10-100 nanometers that were suspended on a cavity to cut off the bypass of the heat current and secure the temperature difference across the silicon nanowires. The cavity structure weakened the mechanical strength of the devices and increased the fabrication cost.

Conventional thermoelectric generator (left) and newly developed thermoelectric generator (right).

To address these problems, a silicon-nanowire thermoelectric generator was developed that experimentally demonstrated a high power density of 12 microwatts per 1 cm2 — enough to drive sensors or realize intermittent wireless communication — at a small thermal difference of only 5 °C.

Because the generator uses the same technology to manufacture semiconductor integrated circuits, its processing cost could be largely cut through mass production. It also could open up a pathway to various autonomously driven IoT devices utilizing environmental and body heat; for example, it may be possible to charge a smartwatch while jogging.

The thermoelectric generator lost the cavity structure, but instead shortened the silicon nanowires to 0.25 nanometer, since simulations showed that the thermoelectric performance improved by minimizing the device. Despite its new structure, the generator demonstrated the same power density as the conventional devices. Thermal resistance was suppressed, and the power density multiplied by ten times by thinning the generator's silicon substrate from the conventional 750 nanometers to 50 nanometers with backside grinding.

For more information, contact Professor Takanobu Watanbe at This email address is being protected from spambots. You need JavaScript enabled to view it..

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This article first appeared in the March, 2019 issue of Tech Briefs Magazine.

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