Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs.

A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other — that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2).

Figure 1. In this G4-FET, the top gate plays the same role as does the sole gate in a conventional accumulation-mode MOSFET. The side gates (JG1 and JG2) provide additional degrees of freedom for design and operation, beyond those of a conventional MOSFET.

By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following:

  • The input and output voltages are differential,
  • The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and
  • The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage.
Figure 2. These Two G4-FET Analog Multiplier Circuits are examples of implementation of four-quadrant multipliers using fewer transistors than were previously required for such multipliers.

The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits.

In experimental versions of these circuits constructed using discrete G4-FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

This work was done by Mohammad Mojarradi, Benjamin Blalock, Sorin Christoloveanu, Suheng Chen, and Kerem Akarvardar of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs. com/tsp under the Semiconductors & ICs category.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:

Innovative Technology Assets Management
JPL
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
(818) 354-2240
E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.

Refer to NPO-41586, volume and number of this NASA Tech Briefs issue, and the page number.

Topics:
Electronic equipment Fabrication Manufacturing processes Semiconductors Semiconductors & ICs Transistors
This Brief includes a Technical Support Package (TSP).
Document cover
Four-Quadrant Analog Multipliers Using G4-FETs

(reference NPO-41586) is currently available for download from the TSP library.

Don't have an account?

Magazine cover
NASA Tech Briefs Magazine

This article first appeared in the December, 2006 issue of NASA Tech Briefs Magazine (Vol. 30 No. 12).

Read more articles from the archives here.

Overview

The document is a Technical Support Package from NASA's Jet Propulsion Laboratory, focusing on a novel technology involving four-quadrant analog multipliers that utilize SOI (Silicon-On-Insulator) Four-Gate Transistors (G4-FETs). This innovation is documented under NASA Tech Brief NPO-41586 and is part of the agency's Commercial Technology Program, which aims to disseminate aerospace-related developments with potential wider technological, scientific, or commercial applications.

The primary focus of the document is on the G4-FET-based analog multiplier circuit, which represents a significant advancement in analog signal processing. The technology was presented by a team of researchers, including K. Akarvardar, S. Chen, B. J. Blalock, S. Cristoloveanu, P. Gentil, and M. Mojarradi, at the ESSCIRC conference in Grenoble, France, in 2005. The G4-FETs are designed to enhance the performance of analog multipliers, which are critical components in various electronic systems, including communication devices, signal processing equipment, and control systems.

The document emphasizes the potential applications of this technology beyond aerospace, suggesting that it could be beneficial in commercial electronics and other fields requiring efficient analog signal manipulation. The G4-FETs are noted for their ability to operate effectively in four-quadrant multiplication, which is essential for applications that require both positive and negative signal processing.

Additionally, the Technical Support Package provides information on how to access further resources related to this technology through the NASA Scientific and Technical Information (STI) Program Office. It includes contact details for the NASA STI Help Desk, offering support for those interested in exploring the research and technology in this area.

The document also includes a disclaimer stating that the United States Government and its representatives do not assume liability for the use of the information contained within, nor do they guarantee that such use will be free from privately owned rights. This highlights the importance of compliance with applicable regulations when utilizing the technology discussed.

In summary, the Technical Support Package presents a cutting-edge development in analog multiplier technology using G4-FETs, with implications for both aerospace and broader commercial applications, while also providing avenues for further inquiry and exploration of the technology.