The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, Vsel •
Specifically, the circuit acts as
- A NAND gate at Vsel=0.0V,
- A wire (the output equals one of the inputs) at Vsel=1.0V, or
- An AND gate at Vsel=-1.8V.
[The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8V.]
{ntbad}
Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package — Genetic Algorithms for Circuit Synthesis (GACS) — that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit.
As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following:
- This circuit contains only 9 transistors — about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library.
- If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.
This work was done by Ricardo Zebulum and Adrian Stoica of Caltech for NASA’s Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Semiconductors & ICs category.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:
Innovative Technology Assets Management
JPL
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
(818) 354-2240 E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.
Refer to NPO-40919, volume and number of this NASA Tech Briefs issue, and the page number.
This Brief includes a Technical Support Package (TSP).
Three-Function Logic Gate Controlled by Analog Voltage
(reference NPO-40919) is currently available for download from the TSP library.
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Overview
The document presents a technical support package detailing NASA's development of a Three-Function Logic Gate Controlled by Analog Voltage. This innovative circuit is designed to perform three distinct logic functions—NAND, AND, and WIRE—using only nine transistors, which is significantly fewer than conventional designs that typically require double the number of components. The primary advantage of this technology lies in its ability to reduce routing area and the number of pins needed, as it utilizes a single analog control line to select different functions.
The document includes various figures illustrating the circuit's performance, including its input and output characteristics for each logic function. Notably, the maximum switching speed of the gate is reported to be 33 MHz (30 ns) for the WIRE function, with propagation delays of approximately 30 ns for the NAND function and 20 ns for the AND function. In comparison, conventional NAND and AND gates exhibit a propagation delay of around 10 ns.
The performance comparison highlights that while the proposed circuit has slower switching speeds and higher dynamic dissipation (1,000 µA) compared to conventional gates (500 µA), it operates effectively without static dissipation. The document emphasizes that the proposed circuit's speed and dissipation are within the same order of magnitude as conventional designs, making it a viable alternative for reconfigurable digital chips.
Additionally, the technology offers faster reconfiguration times compared to commercial FPGAs, which typically require lengthy processes to download large bitstrings. The ability to change functionality at electronic speeds through simple voltage adjustments enhances the circuit's practicality for various applications.
In summary, this document outlines a significant advancement in digital circuit design, showcasing a three-function logic gate that balances performance and efficiency. The proposed technology not only demonstrates the potential for reduced component usage but also opens avenues for faster reconfiguration in digital systems, making it a noteworthy contribution to the field of electronics and aerospace technology.
