The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that has been designed to function as a NAND gate at a temperature between 0 and 80 °C and as a NOR gate at temperatures from 120 to 200 °C. In the intermediate temperature range of 80 to 120 °C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics — a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.
A more extensive discussion of polymorphic electronics was presented in “Polymorphic Electronic Circuits” (NPO-21213), NASA Tech Briefs, Vol. 28, No. 4 (April 2004), page 38. To recapitulate: The traditional approach to design is abandoned in favor of an evolutionary approach to impart the desired multiple functionality to a circuit. In the evolutionary approach, one designs, constructs, and tests a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The evolution is guided by a search-and-optimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality.
In the evolutionary approach, a circuit design can be tested by computational simulation, tested in real hardware, or tested in random sequences of computational simulation and real hardware. In the present case, the designed functionality has been tested thus far by computational simulation and also in real time. The computational simulations have included many tests to assess the robustness of the NAND and NOR gate performances in the presence of noise, for all possible sequences of positive and negative input-signal transitions, and under changes in diverse parameters that include not only temperature but also switching speed, power dissipation, power-supply voltage, transistor sizes, and changes in the transistor model between two commercial fabrication processes. These tests showed the performances to be robust, and once fabricated, the circuit performed as intended. two commercial fabrication processes. These tests showed the performances to be robust, and once fabricated, the circuit performed as intended.
This work was done by Adrian Stoica and Ricardo Zebulum of Caltech for NASA’s Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Semiconductors & ICs category. NPO-30795
This Brief includes a Technical Support Package (TSP).
Multifunctional Logic Gate Controlled by Temperature
(reference NPO-30795) is currently available for download from the TSP library.
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Overview
The document is a technical support package from NASA's Jet Propulsion Laboratory detailing the development of a multifunctional logic gate that operates based on temperature variations. This innovative circuit is designed to function as a NAND gate at lower temperatures and switch to a NOR gate as temperatures increase, showcasing its versatility and adaptability in different operational environments.
The document outlines the testing and performance characteristics of the evolved gate compared to conventional logic gates. It highlights that the NAND functionality exhibits slower performance than the NOR functionality, with the evolved gate's power dissipation being significantly higher—approximately four to five times that of conventional gates. This increased dissipation is attributed to the gate's multifunctional design and the lack of optimization for power consumption.
The robustness of the gate is tested against variations in power supply voltage, demonstrating that it can operate effectively within a range of 1.7V to 2.0V for NAND functionality and 1.6V to 2.0V for NOR functionality without performance degradation. Additionally, the document discusses the sensitivity of the circuit to transistor sizes, revealing that while some transistors cannot be reduced in size without affecting performance, the circuit can tolerate an increase in transistor sizes by up to 1.2μ, suggesting a design margin for enhanced reliability.
The document also compares the driving capabilities of the NOR and NAND functionalities, concluding that the NOR functionality has superior driving capability. It notes that different simulation tools (TSPICE and PSPICE) were used to validate the circuit's performance under varying conditions, ensuring its reliability for future manufacturing.
Overall, this technical support package emphasizes the potential applications of the multifunctional logic gate in aerospace and other fields, where adaptability to temperature changes can enhance circuit performance and reliability. The research represents a significant advancement in logic gate technology, with implications for more efficient and versatile electronic systems. The findings are part of NASA's broader efforts to develop technologies with commercial and scientific applications, contributing to the ongoing evolution of electronic circuit design.
