These architectures are based on methods of vector processing and the discrete Fourier transform/inverse discrete Fourier transform (DFT-IDFT) overlap and save method, combined with time-block separation of digital filters into frequency-domain subfilters implemented by use of sub-convolutions. The parallel processing method implemented in these architectures enables the use of relatively small DFT-IDFT pairs, while filter tap lengths are theoretically unlimited. The size of a DFT-IDFT pair is determined by the desired reduction in processing rate, rather than on the order of the filter that one seeks to implement. A report presents additional information on the parallel, discrete-time, sub-convolution filtering architectures that lie at the heart of the innovation described in "Modular, Parallel, Efficient Pulse-Shaping Filters" (NPO-30186) elsewhere in this issue of NASA Tech Briefs. The emphasis in the report is on those aspects of the underlying theory and design rules that promote computational efficiency, parallel processing at reduced data rates, and simplification of the designs of very-large-scale integrated (VLSI) circuits needed to implement high-order filters and correlators.
This work was done by Andrew A. Gray of Caltech for NASA's Jet Propulsion Laboratory. To obtain a copy of the report, "Computationally Efficient Parallel Subconvolution Filtering Architectures," access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Computers/Electronics category.
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Refer to NPO-30142, volume and number of this NASA Tech Briefs issue, and the page number.
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Parallel Subconvolution Filtering Architectures
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Overview
The document is a NASA Technical Support Package detailing advancements in Parallel Subconvolution Filtering Architectures, prepared under the sponsorship of the National Aeronautics and Space Administration (NASA) and authored by Andrew A. Gray from the Jet Propulsion Laboratory (JPL). It addresses the challenges associated with implementing high-order digital filters in hardware, particularly the complexity and high transistor count required for traditional methods.
The primary focus of the document is on a novel architecture that allows for the implementation of very large scale integration (VLSI) with parallel processing capabilities. This approach significantly reduces the computational and hardware complexity compared to conventional serial convolution methods. The architecture utilizes the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) in a parallel processing framework, enabling the design of high-order finite impulse response (FIR) filters with relatively simple hardware requirements.
The document outlines the motivation behind this development, which stems from the need for efficient processing in high-rate systems. Traditional implementations of large tap length digital filters are often cumbersome and resource-intensive. The proposed solution involves breaking down convolutions into multiple subconvolutions, each processed in the frequency domain. This method allows for the use of smaller DFT-IDFT pairs, making it feasible to implement filters of theoretically unlimited order without a proportional increase in complexity.
The document also emphasizes the advantages of this new architecture, including lower power consumption and reduced design complexity. By employing a parallel approach, the processing rate can be significantly lowered while maintaining high performance, making it suitable for various applications in digital signal processing.
In summary, the document presents a significant advancement in digital filtering technology, showcasing a method that simplifies the implementation of complex filters while enhancing processing efficiency. The work is positioned as a valuable contribution to the field, with potential applications in high-rate systems that require robust and efficient filtering solutions. The findings are intended to support further research and development in digital signal processing and related areas.
